NAND Memory Double SLC Programming with Selective Channel Discharge

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Solution Overview

Problem

Existing memory devices face increased latency in programming operations due to the need for multiple programming pulses and verify phases, especially in high-priority and time-sensitive single level cell (SLC) programming, which affects performance in non-volatile memory devices like NAND flash.

Innovation Solution

Implementing a double single level cell (SLC) program operation where control logic applies a single programming pulse to multiple sub-blocks by boosting the channel voltage and selectively discharging it based on the data pattern, allowing concurrent programming of memory cells in two or more sub-blocks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple programming pulses are used to program memory cells in separate sub-blocks, then programming completeness is improved, but latency increases

Engineering Contradiction:

Improveprogramming completenessVSAvoidlatency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent merges the programming operations of multiple sub-blocks into a single programming pulse operation. By boosting the channel voltage to a higher level that can simultaneously program memory cells across multiple sub-blocks, the system eliminates the need for sequential programming pulses, thereby reducing latency while maintaining programming completeness.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent applies preliminary channel voltage boosting before the programming pulse is applied. This preliminary action prepares the memory device by elevating the channel voltage to a state where a single subsequent programming pulse can effectively program multiple sub-blocks simultaneously, rather than requiring multiple separate programming operations.

Inventive Principle:

Principle #10Preliminary action

2Productivity

If a single programming pulse is applied to multiple sub-blocks concurrently, then productivity is improved, but control precision becomes more difficult

Engineering Contradiction:

Improveprogramming throughputVSAvoidcontrol precision

Core Design Contradiction:

ProductivityVSDifficulty of detecting and measuring

Solution Approach 1:

The patent applies local quality by selectively discharging the boosted channel voltage in specific sub-blocks based on the data pattern requirements. Different sub-blocks receive different treatments (discharge or retain voltage) according to their specific programming needs, allowing precise control over which memory cells are programmed while maintaining the benefit of concurrent operation across multiple sub-blocks.

Inventive Principle:

Principle #3Local quality

3Speed

If channel voltage is boosted to program multiple sub-blocks simultaneously, then speed is improved, but energy consumption increases

Engineering Contradiction:

Improveprogramming speedVSAvoidenergy consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The patent uses partial action by selectively discharging the boosted channel voltage only in the sub-blocks that require programming according to the data pattern. This approach avoids the excessive energy consumption that would result from maintaining high voltage across all sub-blocks, while still achieving the speed benefit of simultaneous programming capability.

Inventive Principle:

Principle #16Partial or excessive action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces the number of program operations required, thereby decreasing latency and improving SLC programming performance by enabling simultaneous programming of multiple sub-blocks, thus enhancing overall memory device efficiency.

Implementation Method 1

boosting the channel voltage and selectively discharging it based on the data pattern

Methodology Applied

Scientific EffectVoltage boosting and selective discharge: Electric Field

Data Source

PatentUS20260011370A1Double single level cell program in a memory device

Publication Date: 2026.01.08 MICRON TECHNOLOGY INC

AI summary

Control logic in a memory device causes a pass voltage to be applied to a plurality of wordlines of a block of a memory array of the memory device, the block comprising a plurality of sub-blocks, and the pass voltage to boost a channel potential of each of the plurality of sub-blocks to a boost voltage. The control logic further selectively discharges the boost voltage from one or more of the plurality of sub-blocks according to a data pattern representing a sequence of bits to be programmed to respective memory cells of the plurality of sub-blocks. In addition, the control logic causes a single programming pulse to be applied to a selected wordline of the plurality of wordlines of the block to program the respective memory cells of the plurality of sub-blocks according to the data pattern.