Semiconductor Integrated Circuit Reset Command Handling
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Solution Overview
Problem
In semiconductor integrated circuits, particularly in flash memory devices, the command-masking period restricts the timing for reset operations, leading to delayed response speeds for command signals during data input and output operations.
Innovation Solution
A semiconductor integrated circuit design that includes a clock pulse generating circuit, a command interface circuit, and a target operating circuit, which generates a command enable clock pulse during the command-masking period upon detection of a reset command, allowing immediate reset operations by adjusting the transition time of flag signals and enabling pulse generation for internal command signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the command-masking period is enforced to prevent command input during data transfer, then data transfer reliability is improved, but reset operation response speed deteriorates
Solution Approach 1:
The patent applies local quality by creating different command acceptance rules for different command types. Specifically, reset commands are allowed to break through the command-masking period restriction while other commands continue to respect the masking period. This is achieved by detecting whether the input command is a reset command and selectively enabling command acceptance based on this detection, thus providing localized exception handling that improves reset response without compromising overall data transfer reliability.
Solution Approach 2:
The patent implements dynamics by making the command-masking period configurable and adjustable based on system state. The command masking period setting unit can dynamically adjust the duration and enforcement of the command-masking period based on whether a reset operation is needed. This allows the system to transition between strict masking mode (for normal data transfer) and relaxed masking mode (for reset operations), optimizing both reliability and response speed under different conditions.
2Reliability
If the command-masking period is extended to ensure complete data transfer, then data transfer completeness is improved, but command processing time increases
Solution Approach 1:
The patent applies preliminary action by detecting reset commands before the command-masking period fully takes effect. The command detecting unit monitors for reset commands during the masking period and, upon detection, triggers immediate command acceptance without waiting for the masking period to expire. This preliminary detection and selective bypass mechanism allows the system to maintain complete data transfer for normal operations while avoiding unnecessary delays for reset operations.
Data Source
AI summary
A semiconductor integrated circuit includes a clock pulse generating circuit suitable for outputting a command enable clock pulse when a predetermined command is input during a predetermined command-masking period, a command interface circuit suitable for outputting an internal command signal based on the command enable clock pulse and the command, and a target operating circuit suitable for performing an operation corresponding to the command based on the internal command signal.