3D Memory Write Voltage Control for Data Retention Stability
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Solution Overview
Problem
Existing semiconductor memory devices with three-dimensional structures face challenges in improving operation reliability, particularly in maintaining data retention characteristics and reducing program disturbance in memory cells due to varying bit storage capacities.
Innovation Solution
The semiconductor memory device employs a control circuit that varies the transfer voltage based on the number of bits being written during a write operation, using a lower transfer voltage for single-level cell mode compared to multi-level cell mode to equalize program disturbance and enhance data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a uniform transfer voltage is applied to all conductive layers during write operation, then the control circuit operation is simplified, but program disturbance varies across different bit storage modes leading to deteriorated data retention characteristics
Solution Approach 1:
The control circuit dynamically adjusts the transfer voltage applied to conductive layers based on the bit storage mode (SLC or MLC) of the memory cells being written. Specifically, when writing to SLC memory cells, a first transfer voltage is applied, and when writing to MLC memory cells, a second transfer voltage different from the first is applied. This dynamic voltage adjustment resolves the contradiction by adapting the operation parameters to the specific storage mode, thereby maintaining data retention characteristics while managing control complexity.
Solution Approach 2:
The invention changes the electrical parameter (transfer voltage) of the control circuit based on the memory cell type. The control circuit is configured to apply different transfer voltages depending on whether the memory cells are operating in SLC or MLC mode. This parameter change allows the system to optimize program disturbance equalization across different bit storage capacities, improving data retention without requiring complete operational simplification.
2Adaptability or versatility
If the semiconductor memory device supports multiple bit storage modes (SLC and MLC), then storage capacity and versatility are improved, but program disturbance equalization becomes difficult leading to reduced operation reliability
Solution Approach 1:
The control circuit applies different transfer voltages to different groups of conductive layers based on their associated memory cell types. Memory cells configured for SLC mode receive one transfer voltage, while memory cells configured for MLC mode receive a different transfer voltage. This localized quality approach allows the system to maintain optimal program disturbance equalization for each storage mode while supporting both modes simultaneously, thereby improving overall operation reliability without sacrificing versatility.
Data Source
AI summary
A semiconductor memory device includes a stacked body in which conductive layers are stacked with an insulating layer interposed therebetween, a semiconductor film to provide a channel for a plurality of memory cell transistors having gates electrically connected to the conductive layers of the stacked body, respectively, an insulating film extending in the stacking direction between the conductive layers and the semiconductor film, and a control circuit configured to control a program voltage to be applied to a conductive layer electrically connected to a memory cell transistor that is a target of a write operation, and a transfer voltage to be applied to conductive layers electrically connected to other memory cell transistors that are not the target of the write operation, wherein the control circuit is configured to vary the transfer voltage to be applied depending on a number of bits that are being written in the write operation.