NAND Memory I/O Timing for Parallel Die Operation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor systems face performance degradation due to increased command overhead in NAND interfaces and difficulty in parallel operations of NAND flash memory devices, particularly in SCA interface methods.
Innovation Solution
A semiconductor apparatus and system design that includes a memory cell array, control circuit, and data input/output circuit, utilizing chip enable and command address signals to manage independent data input/output periods for multiple memory dies, allowing parallel operations without overlapping data input/output periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If NAND interface method is used to transmit command address signal and data through the same input/output bus, then device complexity is reduced, but command overhead increases causing performance degradation
Solution Approach 1:
The patent segments the interface operations by introducing separate command address signal transmission periods and data transmission periods. The command address signal is transmitted during a first period while data is transmitted during a second period, effectively dividing the shared bus usage into distinct time segments. This reduces command overhead and improves system performance while maintaining the simplicity of a shared bus structure.
2Productivity
If separate command address (SCA) interface method is used to transmit command address signal and data through different input/output buses, then command overhead decreases, but parallel operations of multiple NAND flash memory devices become difficult
Solution Approach 1:
The patent implements dynamic bus sharing by allowing the same input/output bus to be dynamically allocated for different purposes at different times. During the first period, the bus is dedicated for command address signal transmission, while during the second period, it is dedicated for data transmission. This dynamic time-division approach enables multiple NAND flash memory devices to operate in parallel while maintaining reduced command overhead.
3Productivity
If multiple memory dies operate in parallel, then productivity increases, but data input/output period management becomes complex
Solution Approach 1:
The patent employs periodic action by establishing distinct first and second periods for different data input/output operations. Multiple memory dies can operate in parallel by alternating between these periods, with each die being selectively enabled during appropriate periods. This periodic structure simplifies the management of data input/output periods while maintaining high parallel operation throughput.
Data Source
AI summary
A semiconductor system includes a first semiconductor apparatus and a second semiconductor apparatus. The first semiconductor apparatus provides the second semiconductor apparatus with a chip enable signal and a command address signal set, and the second semiconductor apparatus performs an internal operation based on the chip enable signal and the command address signal set. The first semiconductor apparatus provides the second semiconductor apparatus with a selection chip enable command, and the second semiconductor apparatus transmits data to the first semiconductor apparatus or receives the data from the first memory device after receiving the selection chip enable command.