Multilayer Charge-Trap Synapse for Linear, Fast Weight Updates
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Solution Overview
Problem
Current neuromorphic computing systems face limitations in linearity and speed when updating synaptic weights, particularly with charge trap memory devices, which affects learning and inference accuracy and speed.
Innovation Solution
A synapse device with a multilayer charge trap layer structure, comprising a shallower first silicon nitride layer and a deeper second silicon nitride layer, forming Schottky junctions, enhances synaptic weight update speed and linearity, and is compatible with CMOS technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If charge trap memory is used for synaptic weight adjustment, then nonvolatile computing-in-memory is achieved, but linearity of conductance modulation deteriorates and weight update speed decreases
Solution Approach 1:
The charge trap layer is divided into multiple trap layers with different trap levels (first trap layer with shallower level, second trap layer with deeper level). This segmentation allows different regions to contribute differently to conductance modulation, improving linearity while maintaining nonvolatile operation
Solution Approach 2:
Different trap layers are assigned different trap levels and material compositions (Si-rich silicon nitride for first layer, N-rich silicon nitride for second layer) to create localized functional differences. This enables precise control over charge trapping and release characteristics in different regions of the device
2Reliability
If charge trap memory is used for synaptic weight adjustment, then nonvolatile computing-in-memory is achieved, but weight update speed decreases
Solution Approach 1:
The charge trap layer is segmented into multiple trap layers with different trap levels. The first trap layer with shallower level enables faster charge release for rapid weight updates, while the second trap layer with deeper level provides stable charge storage for nonvolatile operation
Solution Approach 2:
The multilayer trap structure enables dynamic control over charge release rates. By adjusting which trap layers are activated during potentiation and depression operations, the device can switch between fast update modes (using first trap layer) and stable retention modes (using second trap layer)
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The synapse device improves synaptic weight update speed and linearity, maintaining excellent charge retention characteristics and process compatibility with CMOS technology, making it suitable for neuromorphic devices and neural networks.
Implementation Method 1
the first trap layer has a trap of a shallower level than that of the second trap layer
Implementation Method 2
the source and the first conductor form a Schottky junction, and the drain and the second conductor may form a Schottky junction
Data Source
AI summary
A synapse device, a manufacturing method thereof, and a neuromorphic device including the synapse device are disclosed. The synapse device may include a channel member, a tunnel insulating layer disposed on the channel member, a charge trap layer disposed on the tunnel insulating layer, a blocking insulating layer disposed on the charge trap layer, a gate electrode disposed on the blocking insulating layer, a first terminal and a second terminal respectively connected to first and second regions of the channel member, and first and second conductors respectively bonded to the first and second terminals The charge trap layer may have a multilayer structure including a first trap layer disposed adjacent to the channel member and a second trap layer disposed adjacent to the gate electrode. The first trap layer may have a trap of a shallower level than that of the second trap layer.