Non-Volatile Memory Erase Verify Voltage Control
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Solution Overview
Problem
Existing non-volatile memory devices face challenges in efficiently erasing memory cells, leading to high current and power consumption during the erase operation, which can be detrimental to battery life and overall device performance.
Innovation Solution
The proposed solution involves an apparatus and method for operating non-volatile memory devices, where memory cells connected to word lines are configured to store threshold voltages. A control means applies erase pulses and an erase verify voltage to determine if the threshold voltage of memory cells is below a certain level, maintaining the erase verify voltage throughout multiple iterations to reduce peak current and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional erase operations are used in non-volatile memory devices, then memory cells can be erased, but peak current and power consumption become excessively high
Solution Approach 1:
The patent applies periodic action by dividing the erase operation into multiple iterations with alternating erase pulses and verify operations. Instead of applying a single continuous high-current erase pulse, the system applies erase pulses periodically interspersed with verify pulses that detect whether memory cells have reached the target erased state. This periodic approach allows the system to monitor progress and terminate early when erase is complete, significantly reducing total energy consumption while maintaining reliable erase functionality.
Solution Approach 2:
The patent implements feedback by using verify operations to detect the threshold voltage of memory cells during the erase process. The verify operation provides feedback information about whether memory cells have reached the target erased state (threshold voltage below verify voltage level). This feedback enables the control system to make informed decisions about continuing or terminating the erase operation, preventing unnecessary energy consumption from redundant erase pulses while ensuring complete erase when needed.
2Reliability
If multiple erase verify iterations are performed to ensure complete erase, then erase reliability improves, but power consumption increases due to repeated voltage application
Solution Approach 1:
The verify operation provides feedback information about whether memory cells have reached the target erased state. This feedback enables the control system to make informed decisions about continuing or terminating the erase operation, preventing unnecessary energy consumption from redundant verify iterations while ensuring complete erase when needed.
Solution Approach 2:
The memory cells themselves provide information about their erased state through the verify operation. By measuring the threshold voltage during verify iterations, the system allows the memory cells to self-report whether they have reached the target state, eliminating the need for complex external detection circuits and reducing overall system energy consumption.
3Reliability
If high voltage pulses are applied continuously to ensure complete erase of all memory cells, then erase completeness is guaranteed, but peak current consumption becomes detrimental to battery life
Solution Approach 1:
The system applies erase pulses periodically rather than continuously, interspersing them with verify operations. This periodic application allows the system to monitor progress and terminate early when erase is complete, significantly reducing peak current consumption over time while maintaining erase completeness through iterative verification.
Solution Approach 2:
The verify operation provides feedback information about whether memory cells have reached the target erased state. This feedback enables the control system to make informed decisions about continuing or terminating the erase operation, preventing unnecessary energy consumption from redundant erase pulses while ensuring complete erase when needed.
Data Source
AI summary
A memory apparatus includes memory cells each connected to word lines. The memory cells store a threshold voltage and are disposed in memory holes each defining a channel. The memory holes are grouped into a plurality of strings. A control means is configured to apply at least one erase pulse to the channel of the memory holes of all of the plurality of strings. The control means applies an erase verify voltage to the word lines and successively determine whether at least some of the memory cells of ones of the plurality of strings being erased have the threshold voltage below the erase verify voltage in a plurality of subsequent erase verify iterations. The application of the erase verify voltage to the word lines is maintained constantly throughout an entire duration of the plurality of subsequent erase verify iterations for the at least some of the memory cells.