NAND Multi-Plane Read Synchronization for Lower Noise and Die Area
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Solution Overview
Problem
3D NAND memory devices face challenges in achieving high density and efficient read operations due to the significant die area occupied by sense related circuits and power supply circuits, leading to noise interference and increased read times in asynchronous multi-plane operations.
Innovation Solution
Implementing synchronous independent plane read operations with shared power and ground planes, aligning sense read operations across planes to avoid noise interference, and using a single charge pump and voltage regulator for multiple planes, reducing the need for separate power sources and control circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If separate power supply circuits and sense circuits are provided for each plane to enable independent read operations, then read operation independence is improved, but die area increases and noise interference occurs
Solution Approach 1:
The patent merges power supply circuits and sense circuits into shared resources across multiple planes. A single charge pump circuit generates voltages for multiple planes, and sense circuits are time-multiplexed to serve different planes sequentially, eliminating the need for separate dedicated circuits per plane while maintaining read operation capability.
Solution Approach 2:
The patent implements dynamic time-multiplexing of sense circuits and power supply circuits. The sense circuits are dynamically allocated to different planes based on read operation timing, allowing the same physical circuits to serve multiple planes at different time intervals, thus reducing die area while preserving functional independence.
2Object-affected harmful factors
If separate power supply circuits are provided for each plane, then noise interference is reduced, but die area and device complexity increase
Solution Approach 1:
The patent segments the operation timing into distinct time intervals for different planes. By carefully controlling the timing of read operations on different planes, the patent ensures that sense operations occur at non-overlapping times, thereby segmenting noise sources in the time domain rather than requiring spatial separation through separate circuits.
Solution Approach 2:
The patent employs periodic time-multiplexed operation where sense circuits are activated in periodic cycles for different planes. Each plane receives dedicated sense circuit access during its assigned time window in a periodic sequence, ensuring noise-free operations while using shared hardware resources.
3Speed
If asynchronous multi-plane read operations are implemented, then read speed is improved, but noise interference and read time variation increase
Solution Approach 1:
The patent dynamically schedules read operations across multiple planes with synchronized timing control. The system adapts the timing of sense operations for different planes to ensure they occur at optimal moments when noise interference is minimized, while maintaining the asynchronous nature of plane selection to preserve high read speeds.
Data Source
AI summary
An embodiment of an apparatus may include NAND memory organized as two or more memory planes and a controller communicatively coupled to the NAND memory, the controller including circuitry to provide synchronous independent plane read operations for the two or more memory planes of the NAND memory. Other embodiments are disclosed and claimed.