Partial Write-Back Module for SRAM Bit Line Biasing
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Solution Overview
Problem
SRAM cell architectures face challenges in reducing operating power consumption, particularly during write cycles, as half-selected cells are prone to upset, leading to increased dynamic power usage and delayed data arrival in non-selected columns due to full bit line swings.
Innovation Solution
The implementation of a partial write-back module that establishes a bit line bias based on the current state of memory cells during a read operation, reducing the bit line swing in half-selected cells to prevent upset without flipping their state, thereby lowering power consumption and reducing delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If read and write-back is used to preserve the state of half-selected cells during a write cycle, then cell upset is prevented, but dynamic power consumption increases considerably
Solution Approach 1:
The patent applies partial write-back by performing write-back operations only on half-selected cells rather than all cells in the array. This selective approach maintains the current state of half-selected cells to prevent upset while avoiding the full power consumption of a complete write-back operation across the entire memory array.
Solution Approach 2:
The invention implements local write-back by targeting specific half-selected cells that are prone to upset during write operations. Instead of applying a uniform write-back strategy to the entire array, the patent selectively applies write-back only where needed (in half-selected cells), thereby reducing overall power consumption while maintaining reliability where required.
2Productivity
If full bit line swings are performed during write cycles, then data is written to selected cells, but delay occurs in non-selected columns and power consumption increases
Solution Approach 1:
The patent performs bit line swings only for selected cells that require writing, rather than applying full bit line swings to all columns. This partial action approach maintains write speed for selected cells while eliminating unnecessary delays and power consumption in non-selected columns.
Solution Approach 2:
The invention applies different bit line swing characteristics to different cell types: full swings for selected cells requiring writing, and no swing or minimal activity for non-selected columns. This localized approach optimizes both write speed and timing by tailoring the bit line behavior to the specific needs of each cell group.
Data Source
AI summary
An integrated circuit having a functional memory and methods of operating and reducing an operating power of the integrated circuit are provided. The functional memory includes an array of memory cells connected to row and column periphery units and organized in corresponding rows and columns. The memory also includes a word line that provides row access to a memory cell. The memory further includes at least one bit line that provides column access to the memory cell. The memory still further includes a partial write-back module, connected to the at least one bit line, that establishes a bit line bias to maintain a current state of the memory cell when in a half-selected condition based on a read of the current state and during a write cycle to a selected memory cell in the array.