Split-Gate Twin-Bit Memory Cell With Continuous Shared Channel
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Solution Overview
Problem
The complexity and performance limitations of existing split-gate non-volatile flash memory cell architectures, particularly in shrinking dimensions, due to the need for multiple electrodes and channel regions, make them difficult to configure and implement effectively.
Innovation Solution
A two-bit memory cell design with a continuous channel region and shared word line gate, featuring floating gates, coupling gates, and erase gates, which are insulated and strategically positioned to enhance voltage coupling and erase operations, allowing for simultaneous erasure and bit-selectable programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional split-gate flash memory cells use separate channel regions for each memory cell, then each cell can store one bit of information, but the architecture becomes overly complex and difficult to implement as critical dimensions shrink
Solution Approach 1:
The patent merges two separate channel regions into a single continuous channel region that serves both memory cells. This continuous channel region extends from the first drain region through the second drain region, allowing both memory cells to share common infrastructure while maintaining individual functionality for storing two bits of information total.
Solution Approach 2:
The continuous channel region performs multiple functions: it serves as the conduction path for both memory cells simultaneously, provides a shared region for voltage coupling during programming and erasing operations, and enables the memory cell structure to store two bits of information rather than one. The single continuous channel region replaces what would traditionally require two separate channel regions.
2Device complexity
If memory cells share a common source region and continuous channel region, then device complexity is reduced, but erase gate functionality and voltage coupling performance are compromised
Solution Approach 1:
The patent segments the gate structure into distinct functional components: a select gate positioned over the first drain region for controlling the first memory cell, a control gate positioned over the continuous channel region for voltage coupling, and an erase gate positioned over the second drain region for erasing the second memory cell. This segmentation allows each gate to perform its specific function effectively despite the shared channel region.
Solution Approach 2:
The patent applies different gate structures and materials at different locations along the continuous channel region. The select gate, control gate, and erase gate are positioned at specific locations with different functions. The gate materials and insulating layers are optimized locally for each function, with the control gate having enhanced coupling to the floating gates for voltage delivery during programming operations.
3Productivity
If critical dimensions are shrunk to increase memory density, then more memory cells can be packed, but configuring and forming the architecture with multiple electrodes becomes increasingly difficult
Solution Approach 1:
The patent merges infrastructure elements to reduce the number of components that must be fabricated at shrinking dimensions. The continuous channel region replaces two separate channel regions, and the shared select gate and control gate structures reduce the total electrode count. This merging reduces fabrication steps and aligns better with standard semiconductor manufacturing processes, making it easier to manufacture high-density memory arrays.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design simplifies the architecture, improves voltage coupling, and enables efficient programming and erasure of two bits per memory cell, addressing the complexity and performance limitations of previous configurations while allowing for scalable and reliable memory cell arrays.
Implementation Method 1
strategically positioned to enhance voltage coupling and erase operations
Implementation Method 2
A current path is established between the first and second drain regions when a voltage is applied between a control gate and the continuous channel region
Implementation Method 3
floating gates, coupling gates, and erase gates, which are insulated and strategically positioned
Data Source
Figure 1A
Figure 1B
Figure 1C
AI summary
A memory device that includes a substrate of semiconductor material of a first conductivity type, first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a continuous channel region in the substrate extending between the first and second regions. A first floating gate is disposed over and insulated from a first portion of the channel region adjacent to the first region. A second floating gate is disposed over and insulated from a second portion of the channel region adjacent to the second region. A word line gate is disposed over and insulated from a third portion of the channel region between the first and second channel region portions. A first erase gate disposed over and insulated from the first region. A second erase gate disposed is over and insulated from the second region.