eFuse Memory Cell Array With Shared Program and Read Path
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Solution Overview
Problem
Conventional eFuse implementation in non-volatile memory devices requires overcurrent for programming, leading to increased area per unit cell and overall device size due to separate paths for program and read currents.
Innovation Solution
A non-volatile memory device with a fuse-type cell array that steers program and read currents through the same path using a switching element, such as an NMOS transistor or diode, reducing the number of components per unit cell and optimizing the cell structure to minimize area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate paths are used for program current and read current in conventional eFuse, then the program operation can be performed reliably, but the area of each unit cell increases
Solution Approach 1:
The patent merges the program current path and read current path into a single shared path. The eFuse cell uses the same bit line and eFuse element for both programming and reading operations, eliminating the need for separate dedicated paths. This consolidation directly reduces the unit cell area while maintaining functional reliability through proper operation mode separation.
Solution Approach 2:
The bit line and eFuse element are designed to serve multiple functions: they carry program current during programming operations and carry read current during read operations. This multi-functionality allows the same hardware components to be reused for different operational modes, reducing the overall component count and unit cell footprint without compromising program operation reliability.
2Reliability
If separate paths are used for program current and read current in conventional eFuse, then the program operation can be performed reliably, but the overall device size increases
Solution Approach 1:
The patent merges the program current path and read current path into a single shared path. The eFuse cell uses the same bit line and eFuse element for both programming and reading operations, eliminating the need for separate dedicated paths. This consolidation directly reduces the unit cell area while maintaining functional reliability through proper operation mode separation.
Solution Approach 2:
The bit line and eFuse element are designed to serve multiple functions: they carry program current during programming operations and carry read current during read operations. This multi-functionality allows the same hardware components to be reused for different operational modes, reducing the overall component count and unit cell footprint without compromising program operation reliability.
3Adaptability or versatility
If more components are used in each unit cell to support separate current paths, then the program and read operations can be differentiated, but the quantity of components per unit cell increases
Solution Approach 1:
The patent uses dynamic control through the word line to switch between program and read operations on the same hardware path. The first switching element (NMOS transistor) is controlled by the word line to selectively enable program current flow or read current flow through the shared bit line and eFuse element. This dynamic switching replaces the need for static separate physical paths, reducing component count while maintaining operational differentiation.
Solution Approach 2:
The bit line and eFuse element are designed to serve multiple functions: they carry program current during programming operations and carry read current during read operations. This multi-functionality allows the same hardware components to be reused for different operational modes, reducing the overall component count and unit cell footprint without compromising program operation reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure reduces the area of each unit cell and the overall memory device by integrating program and read operations within a single current path, thereby minimizing the size of the eFuse cell array and the entire chip.
Implementation Method 1
a resistance value of the eFuse is permanently changed to a value different from an initial resistance value before the blowing
Data Source
AI summary
A non-volatile memory device based on a fuse type memory cell array includes an eFuse cell array including a plurality of unit cells in matrix form, each unit cell having a first switching element and an eFuse; an address decoder configured to activate, based on an address input from an external device, a word line used for program operation or read operation among a plurality of word lines; a current controller configured to supply a program current used for the program operation or a read current used for the read operation; a bit line sense amplifier configured to sense digital data output from the eFuse cell array and output the digital data; and a control logic configured to control the program operation or the read operation to be performed based on a control signal input from the external device.