Charge Trap Layer Structure for High-Density Nonvolatile Memory
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Solution Overview
Problem
Current nonvolatile memory devices face challenges in increasing capacity and preventing lateral charge spreading in the charge trap layer, which affects data storage efficiency.
Innovation Solution
A nonvolatile memory device is designed with a charge trap layer made of two-dimensional material having an inclined crystalline structure, alternately stacked with insulating and sacrificial layers, and a charge tunneling layer, to reduce lateral charge spreading and enhance storage density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the capacity of nonvolatile memory devices is increased by increasing cell density, then storage capacity is improved, but lateral charge spreading in the charge trap layer increases causing data storage errors
Solution Approach 1:
The patent applies local quality by creating a charge trap layer with spatially varying properties - specifically, the crystalline structure is oriented perpendicular to the channel layer in regions adjacent to sacrificial layers, while having different orientation in other regions. This local structural differentiation prevents lateral charge spreading at critical interfaces while maintaining storage capacity throughout the device.
Solution Approach 2:
The patent uses composite materials by combining the charge trap layer made of two-dimensional material with sacrificial layers and insulating layers in an alternating stacked structure. This composite architecture allows the charge trap layer to maintain high storage capacity while the integrated sacrificial and insulating layers provide structural support and prevent lateral charge spreading.
2Productivity
If the cell density is increased to improve storage capacity, then storage density is improved, but lateral charge spreading increases reducing memory reliability
Solution Approach 1:
The patent implements local quality by orienting the crystalline structure of the two-dimensional material in the charge trap layer perpendicular to the channel layer specifically in regions adjacent to sacrificial layers. This localized structural arrangement prevents lateral charge spreading at the critical charge trap layer-sacrificial layer interfaces, thereby maintaining memory reliability while allowing increased cell density for higher storage density.
Solution Approach 2:
The patent applies dimensionality change by transitioning from a planar charge trap layer structure to a vertically oriented crystalline structure within the two-dimensional material. This vertical orientation (perpendicular to the channel layer) adds a dimensional aspect that confines charges in the lateral direction, preventing charge spreading while maintaining storage capacity.
3Ease of manufacture
If conventional charge trap layer structures are used to simplify manufacturing, then ease of manufacture is improved, but lateral charge spreading occurs reducing storage efficiency
Solution Approach 1:
The patent applies parameter changes by modifying the crystalline structure orientation parameter of the two-dimensional material in the charge trap layer. Specifically, the crystalline structure is oriented perpendicular to the channel layer in regions adjacent to sacrificial layers, which changes the charge confinement characteristics and prevents lateral charge spreading, thereby improving storage efficiency while maintaining manufacturability through standard fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces lateral charge spreading and increases storage density, enabling more efficient data storage and retrieval in nonvolatile memory devices.
Implementation Method 1
the two-dimensional material may include a region having an inclined crystalline structure with respect to the channel layer
Data Source
AI summary
Provided is a nonvolatile memory device. The nonvolatile memory device includes: a channel layer; a plurality of gate electrodes and a plurality of insulating layers being spaced apart from the channel layer and being alternately arranged; a charge trap layer between the channel layer and a gate electrode, and a charge tunneling layer between the channel layer and the charge trap layer.