3D Memory Gate Stack Barrier Structure Against Contact Over-Etching
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Solution Overview
Problem
As integration density of semiconductor devices increases, electrical characteristics and production yield deteriorate, necessitating improvements in semiconductor device design to enhance reliability and performance.
Innovation Solution
A semiconductor device design featuring alternately stacked first and second gate stacks with insulating and conductive patterns, a memory channel structure, and a barrier pattern surrounding a penetration contact, which includes contact insulating patterns on both sides of the penetration contact, improving structural integrity and reducing the risk of over-etching during fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If integration density of semiconductor devices is increased, then productivity and functionality are improved, but electrical characteristics and production yield deteriorate
Solution Approach 1:
A barrier pattern is introduced as an intermediary structure between the penetration contact and the connection insulating pattern. This barrier pattern prevents direct contact and potential damage to the connection insulating pattern during etching processes, thereby maintaining electrical characteristics while allowing high integration density design
Solution Approach 2:
The barrier pattern is formed in advance before final connection structures are completed. By pre-positioning this protective barrier, the design prevents potential damage to critical insulating patterns during subsequent fabrication steps, ensuring both high integration density and reliable electrical characteristics
2Productivity
If integration density of semiconductor devices is increased, then productivity and functionality are improved, but production yield deteriorates
Solution Approach 1:
The barrier pattern serves as a protective intermediary that prevents over-etching damage to connection insulating patterns. This reduces manufacturing defects and improves production yield while maintaining the high integration density structure
Solution Approach 2:
The barrier pattern provides a cushioning effect by absorbing or preventing etching damage before it can reach the critical connection insulating pattern. This protective measure ensures manufacturing precision is maintained even as integration density increases
3Reliability
If barrier pattern is added to protect connection insulating pattern, then reliability is improved, but device complexity increases
Solution Approach 1:
The barrier pattern is applied locally only where needed - specifically at the interface between the penetration contact and connection insulating pattern. This targeted approach provides necessary protection while minimizing overall device complexity and avoiding unnecessary structural additions
Data Source
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AI summary
A semiconductor device including: a first gate stack including first insulating patterns and first conductive patterns; a second gate stack on the first gate stack, the second gate stack including second insulating patterns and second conductive patterns; a memory channel structure penetrating the first and second gate stacks; a penetration contact penetrating the first and second gate stacks; and a barrier pattern on opposite sides of the penetration contact, the first insulating patterns include a first connection insulating pattern, which is an uppermost one of the first insulating patterns, the second insulating patterns include a second connection insulating pattern which is in contact with a top surface of the first connection insulating pattern, a bottom surface of the barrier pattern is in contact with the top surface of the first connection insulating pattern, and a top surface of the barrier pattern is in contact with the second connection insulating pattern.