Ferroelectric Memory Stack Using Antiferroelectric HZO for Cycle Durability
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Solution Overview
Problem
Ferroelectric memories face challenges with cycle durability and memory window enlargement due to deterioration in ferroelectric films, leading to instability in operation.
Innovation Solution
A nonvolatile semiconductor memory is developed with a structure that includes a ferroelectric layer and an antiferroelectric layer, where the antiferroelectric layer is formed by adding Si or Al to a HZO film in a specific range, enhancing cycle durability and memory window stability by mixing antiferroelectric and ferroelectric substances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a ferroelectric film is used in memory operations, then nonvolatile storage capability is achieved, but cycle durability deteriorates and memory window is lost due to film deterioration
Solution Approach 1:
The patent applies composite materials by forming a ferroelectric layer containing HfZrO film mixed with antiferroelectric domains. This composite structure combines the nonvolatile storage capability of ferroelectric materials with the enhanced stability of antiferroelectric domains, resolving the contradiction between achieving nonvolatile storage and maintaining cycle durability. The specific composition (Hf: 40-70 at%, Zr: 30-60 at%) creates a material system where antiferroelectric domains prevent ferroelectric film deterioration while preserving memory functionality.
Solution Approach 2:
The patent employs parameter changes by precisely controlling the compositional parameters of the HfZrO film (Hf: 40-70 at%, Zr: 30-60 at%) and the density of added elements (Si, Al, Ge, or Ga at 1-6 at%). These parameter adjustments transform the material properties to achieve optimal balance between ferroelectric polarization and antiferroelectric stability, thereby improving cycle durability while maintaining memory window.
2Reliability
If Si or Al is added to HfZrO film to create antiferroelectric domains, then cycle durability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent merges the formation of antiferroelectric domains with the existing ferroelectric layer deposition process. By adding elements (Si, Al, Ge, or Ga) during the ALD process and utilizing a single crystallization annealing step, the patent combines multiple functions (ferroelectric layer formation, antiferroelectric domain creation, and crystallization) into one integrated manufacturing flow, reducing overall process complexity despite the enhanced functionality.
Solution Approach 2:
The patent uses parameter changes to control the formation of antiferroelectric domains through precise adjustment of element density (1-6 at%) and crystallization temperature (600-900°C). By optimizing these parameters, the patent achieves the desired antiferroelectric domain formation without requiring additional complex processing steps, thereby improving cycle durability while managing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves cycle durability and enlarges the memory window, stabilizing the operation of ferroelectric memories by maintaining polarization charges and reducing polarization reversal degradation over a large number of cycles.
Implementation Method 1
Through a thermal process, an antiferroelectric substance that has an orthorhombic crystal as one main component is formed in the first HZO layer 15 and a ferroelectric substance having a tetragonal crystal as one main component is formed in the second HZO layer 13
Data Source
AI summary
A memory cell includes: a core structure extending in a first direction orthogonal to a semiconductor substrate; a semiconductor layer extending in the first direction and in contact with the core structure; an insulating layer extending in the first direction and in contact with the semiconductor layer; a ferroelectric layer extending in the first direction and in contact with the insulating layer; a first electrode extending in a second direction orthogonal to the first direction and in contact with the ferroelectric layer; a second electrode adjacent to the first electrode in the first direction, extending in the second direction, and in contact with the ferroelectric layer; an insulating layer stacked in the first direction and disposed between the first and second electrodes; and an antiferroelectric layer disposed between the first and second electrodes, and in contact with the insulating layer and the ferroelectric layer.