Bit Line Precharge Boosting for Low-Voltage Memory Reads
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor memory devices face challenges in securing a sufficient sensing margin for reading information data during power-up due to decreasing internal voltage levels, which can lead to sensing failures.
Innovation Solution
The implementation of a memory device that utilizes parasitic capacitance coupling between neighboring bit lines to boost the voltage level of one bit line, thereby increasing the sensing margin during an information data read operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If external voltage is decreased to reduce power consumption, then power consumption is reduced, but sensing margin becomes insufficient
Solution Approach 1:
The patent introduces a parasitic capacitor as an intermediary element between the first bit line and second bit line. This capacitor mediates the voltage transfer from the boosted second bit line to the first bit line, enabling the first bit line to achieve a higher voltage level without directly applying high voltage, thus resolving the contradiction between low power consumption and sufficient sensing margin
Solution Approach 2:
The patent employs periodic voltage boosting to the second bit line at specific timing intervals during the read operation. By applying boost voltage periodically rather than continuously, the system achieves necessary voltage levels for sensing while minimizing overall power consumption, resolving the contradiction between sensing margin requirements and power consumption
2Use of energy by stationary object
If internal voltage decreases due to external voltage reduction, then power consumption decreases, but data sensing accuracy deteriorates
Solution Approach 1:
The patent dynamically changes the voltage parameter of the first bit line by utilizing capacitive coupling from the boosted second bit line. This parameter change enables the first bit line to maintain a high voltage level (improving sensing accuracy) while the overall system operates at low external voltage (reducing power consumption), thus resolving the contradiction between power consumption and sensing accuracy
3Reliability
If boost voltage is applied to second bit line, then sensing margin of first bit line is improved, but device complexity increases
Solution Approach 1:
The patent utilizes the naturally occurring parasitic capacitor between adjacent bit lines rather than requiring a separate dedicated capacitor component. This self-service approach leverages existing physical structures to achieve voltage boosting, improving sensing margin without significantly increasing device complexity or requiring additional external components
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures a stable sensing margin, preventing sensing failures and ensuring accurate data read operations even as power consumption decreases.
Implementation Method 1
the precharge voltage level of the first bit line is increased due to a couple cap parasitically existing between the first and second bit lines
Data Source
AI summary
A memory device is disclosed which includes a first bit line connected to a first cell string; a second bit line connected to a second cell string and adjacent to the first bit line; and a bit line precharge controller configured to control voltage levels of the first and second bit lines during an information data read operation to read data stored in the first cell string. The bit line precharge controller precharges the first bit line, provides a boost voltage to the second bit line, and then senses the data stored in the first cell string. The precharge voltage level of the first bit line is increased by the boost voltage provided to the second bit line.