Memory Card Terminal Group Layout for SD And PCIe Lane Skew
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Solution Overview
Problem
As storage capacity increases in memory cards, the data transfer time also increases, necessitating higher-speed communication interfaces to maintain efficient data transfer.
Innovation Solution
The memory card is designed with distinct terminal groups for single-ended and differential signals, allowing it to support multiple communication standards like SD and PCIe, with differential signals assigned to separate rows to facilitate multi-lane configurations, reducing skew and increasing transfer speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If storage capacity is increased, then data transfer amount increases, but data transfer time increases
Solution Approach 1:
The patent segments the terminal connections into distinct first terminal groups for single-ended signals and second terminal groups for differential signals. This segmentation enables simultaneous support for multiple communication standards (SD and PCIe) through separate signal paths, allowing high-speed data transfer without increasing transfer time despite high storage capacity
Solution Approach 2:
The memory card is designed with multi-functionality to support both SD and PCIe communication standards through the same physical interface. The controller can switch between single-ended and differential signal modes, enabling the card to operate at high speeds compatible with both standards, thus maintaining fast data transfer even with large storage capacities
2Speed
If communication interface speed is increased, then data transfer speed improves, but signal skew between lanes increases
Solution Approach 1:
The patent assigns differential signals to separate rows (second rows) distinct from single-ended signal rows. This spatial segmentation in the terminal arrangement allows for better control of signal timing and reduces skew between lanes by isolating differential signal paths, enabling high-speed transfer while maintaining signal integrity
Solution Approach 2:
The patent applies different signal types (single-ended vs differential) to different local regions (rows) of the terminal groups. Differential signals are confined to specific rows with dedicated terminal groups, allowing optimized signal routing and timing control for each region, thereby reducing overall signal skew while maintaining high transfer speeds
3Adaptability or versatility
If multiple communication standards are supported, then adaptability improves, but device complexity increases
Solution Approach 1:
The patent segments the interface into distinct terminal groups for different communication standards - first terminal groups for SD standard single-ended signals and second terminal groups for PCIe differential signals. This segmentation allows the controller to selectively activate the appropriate interface type based on the host device requirements, achieving multi-standard compatibility without requiring all components to be present simultaneously, thus managing complexity
Solution Approach 2:
The memory card incorporates multi-functionality by integrating both SD and PCIe interface capabilities within a single card design. The controller is designed to handle both single-ended and differential signal protocols, allowing one card to serve multiple communication purposes. This universal design improves adaptability across different host devices while the integrated nature of the design manages complexity by combining rather than multiplying separate interface implementations
Data Source
AI summary
According to one embodiment, there is provided a memory card including a first surface, a second surface, and 1st to Nth terminal groups. The first surface includes first to Nth rows, where N is an integer of two or greater. The second surface faces the opposite side from the first surface. The 1st to Nth terminal groups are placed in the first to Nth rows. The 1st terminal group includes terminals to which differential clock signals are assigned, terminals to which single-ended signals are assigned, and a terminal to which a first power supply voltage is assigned. Kth terminal group, where K is an integer no smaller than two and no greater than N, includes terminals to which differential data signals are assigned.