Flash Memory Program Method Using Dummy Pulses
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing program methods for multi-level cell (MLC) flash memory devices result in wide threshold voltage distributions, which negatively impact the reliability of cell operation and prolong program time due to the narrow voltage gap and increased number of incremental step pulse program (ISPP) pulses required.
Innovation Solution
A program method that applies a series of dummy pulses before the ISPP operation to reduce the threshold voltage distribution width, specifically by applying increasing dummy step pulses to a MLC in the state '10' with a wide threshold voltage, followed by a program step pulse and verify operations, and adjusting the voltage if necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the ISPP voltage is lowered to reduce the threshold voltage distribution width, then the threshold voltage distribution width is reduced, but the program time is lengthened due to increased number of pulses required
Solution Approach 1:
The patent applies preliminary action by performing a reset operation before the main ISPP program operation. This reset operation includes applying a reset pulse to initialize the threshold voltage distribution, which prepares the memory cells for subsequent programming. By pre-initializing the cells, the main program operation can proceed more efficiently with fewer pulses, thus reducing overall program time while maintaining tight threshold voltage distribution.
Solution Approach 2:
The patent employs parameter changes by dynamically adjusting the reset pulse voltage and width based on the initial threshold voltage state of the memory cells. The reset operation uses a voltage that is higher than the read verify voltage but controlled to not excessively increase the threshold voltage. This parameter optimization allows the system to achieve narrow threshold voltage distribution without requiring an excessive number of ISPP pulses, thereby balancing precision and speed.
2Adaptability or versatility
If the voltage gap between threshold voltages is narrowed to increase storage capacity, then more bits can be stored per cell, but the reliability of cell operation deteriorates
Solution Approach 1:
The patent applies segmentation by dividing the programming process into two distinct phases: a reset phase and a main ISPP programming phase. The reset phase segments the initial threshold voltage adjustment, creating a controlled starting point with narrower distribution. The main programming phase then segments the voltage increments into smaller, more precise steps. This segmentation allows the system to maintain narrow threshold voltage distribution even with narrow voltage gaps between stored bits, thereby improving reliability while preserving high storage capacity.
Solution Approach 2:
The reset operation serves as a preliminary action that pre-configures the memory cells before main programming. By applying a controlled reset pulse that raises the threshold voltage to a specific level with narrow distribution, the system creates an optimized starting state. This preliminary configuration ensures that subsequent programming operations can reliably distinguish between different threshold voltage levels even when the overall voltage gap is narrow, thus maintaining both high capacity and reliability.
3Manufacturing precision
If the number of ISPP pulses is increased to reduce threshold voltage distribution width, then the threshold voltage distribution width is reduced, but the program time is significantly prolonged
Solution Approach 1:
The reset operation acts as a preliminary action that performs part of the threshold voltage adjustment work before the main ISPP programming begins. By pre-raising the threshold voltage to an intermediate level with controlled distribution width, the reset operation reduces the total voltage range that needs to be covered during main programming. This preliminary work significantly reduces the number of ISPP pulses required, thereby maintaining narrow threshold voltage distribution while improving program speed and productivity.
Solution Approach 2:
The reset operation performs a partial programming action by raising the threshold voltage to an intermediate level rather than completing the full programming range. This partial action is intentional and controlled, creating a starting point that requires fewer subsequent ISPP pulses. The reset uses a voltage that is higher than what would be used for a single-bit program, but controlled to not excessively over-program the cells. This partial action approach optimizes the balance between achieving narrow distribution and maintaining fast programming.
Data Source
AI summary
A method for programming a non-volatile memory device includes applying a first dummy voltage to a Multi-Level Cell (MLC). A first program voltage is applied to the MLC to program the MLC, the first program voltage being applied to the MLC after the first dummy voltage has been applied to the MLC. The MLC is verified whether or not the MLC has been programmed correctly by the first program voltage. A second dummy voltage is applied to the MLC after the first dummy voltage has been applied, the second dummy voltage being N volt higher than the first dummy voltage, wherein the second dummy voltage applied to the MLC is of sufficiently low voltage, so that the second dummy voltage does not change an initial state of the MLC. A third dummy voltage is applied to the MLC after the second dummy voltage has been applied, the third dummy voltage being N volt higher than the second dummy voltage.