OTP Memory Cell Structure for Diode-Effect Read Margin
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Solution Overview
Problem
Conventional one-time programmable (OTP) memory cells experience a diode effect in the read current path after programming, leading to reduced current and margin, and voltage stress on select transistors during programming.
Innovation Solution
Incorporating an additional dopant region under the gate of the anti-fuse transistor and using a cascaded select transistor configuration to reduce diode effect and relax voltage stress, respectively, while also employing shorter gate lengths and specific dopant concentrations to enhance tolerance against voltage stresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional OTP memory cell structure is used, then device simplicity is maintained, but diode effect occurs in read current path reducing read current and margin
Solution Approach 1:
The memory cell is segmented into distinct functional regions: the anti-fuse transistor for programming, select transistors for row/column selection, and an additional dopant region specifically designed to counteract the diode effect. This segmentation allows each component to be optimized for its specific function while working together to solve the overall problem.
Solution Approach 2:
An additional dopant region is introduced locally in the substrate beneath the anti-fuse transistor gate. This localized modification changes the electrical properties in the read current path, creating a more favorable potential distribution that reduces the diode effect without affecting other parts of the memory cell structure.
2Productivity
If conventional programming method is used, then programming function is achieved, but voltage stress is applied to select transistors
Solution Approach 1:
Cascaded select transistors are introduced as intermediary elements between the programming circuitry and the memory array. These additional transistors act as voltage buffers, distributing and reducing the voltage stress that would otherwise be applied directly to the select transistors during programming operations.
Solution Approach 2:
The cascaded select transistor configuration dynamically adjusts voltage distribution during different operating modes (programming vs. reading). During programming, the cascaded structure divides and reduces voltage stress; during reading, the structure maintains proper signal levels while minimizing interference.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The additional dopant region minimizes the diode effect, increasing read current and improving read margin, while the cascaded select transistor configuration reduces voltage stress on select transistors, resulting in improved performance and reliability of OTP memory cells.
Implementation Method 1
An additional fourth dopant region connects to the first dopant region and extends partially under the first gate of the anti-fuse transistor. The additional fourth dopant region forms an additional current path for a read current.
Implementation Method 2
The first transistor is an anti-fuse transistor that receives a word line program (WLP) signal on a gate of the anti-fuse transistor
Data Source
AI summary
Various one-time-programmable (OTP) memory cells are disclosed. An OTP memory cell includes an additional dopant region that extends at least partially under the gate of a transistor, such as an anti-fuse transistor. The additional dopant region provides an additional current path for a read current. Alternatively, an OTP memory cell includes three transistors; an anti-fuse transistor and two select transistors. The two select transistors can be configured as a cascaded select transistor or as two separate select transistors.