Memory Address Scrambling for Row Hammer Attack Resistance
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Solution Overview
Problem
As memory integration increases, the coupling effect between neighboring word lines intensifies, leading to data deterioration and potential damage from row hammering due to frequent activation of word lines, which existing methods like row refreshing are inadequate in addressing.
Innovation Solution
Implementing an address scrambler and scramble control circuit to scramble memory addresses based on a scrambling rule, changing the rule upon detection of an attack condition to thwart row hammering attacks by obscuring the location of sensitive data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory integration increases to improve storage capacity, then storage density is improved, but coupling effect between neighboring word lines increases causing row hammering attacks
Solution Approach 1:
The patent applies dynamics by making the address scrambling rule changeable over time. The scramble control circuit dynamically switches between different scrambling rules based on detected attack conditions, preventing attackers from predicting memory locations even as integration density increases
Solution Approach 2:
The patent changes the scrambling rule parameters in response to detected row hammering attacks. By modifying the scrambling algorithm's parameters (such as the scrambling matrix or seed values), the system alters the mapping between logical and physical addresses, making it impossible for attackers to target specific physical locations through repeated activation
2Speed
If frequent word line activation occurs to improve access speed, then access speed is improved, but data in neighboring memory cells deteriorates due to coupling effect
Solution Approach 1:
The address scrambler acts as an intermediary layer between the controller and memory core. It scrambles addresses before they reach the memory, so that even if frequent activations occur, the actual physical locations being accessed are unpredictable, preventing cumulative damage to specific memory cells
Solution Approach 2:
The system performs preliminary address scrambling before memory access operations. By pre-scrambling addresses and having the ability to switch scrambling rules, the system prepares defenses against row hammering before attacks occur, ensuring data integrity even under frequent access conditions
3Reliability
If address scrambling is implemented to defend against row hammering, then security is improved, but device complexity increases
Solution Approach 1:
The address scrambler is designed to perform multiple functions: normal address translation, row hammering defense through scrambling, and dynamic rule switching. This multi-functionality reduces the need for separate dedicated defense circuits, managing complexity while maintaining security
Solution Approach 2:
The system implements partial scrambling - not all address bits need to be fully scrambled, and not all memory locations require the same level of protection. The scramble control circuit only switches rules when attack conditions are detected, avoiding the complexity of constantly changing rules without providing proportional security benefits
Data Source
AI summary
A memory system includes: an address scrambler suitable for scrambling an address based on a scrambling rule to generate a scrambled address; a memory core including a plurality of memory cells and suitable for storing data in memory cells designated by the scrambled address; and a scramble control circuit suitable for changing the scrambling rule in response to satisfaction of an attack condition.