3D Nonvolatile Memory Device with Layered Drive Circuits

The patent transitions from planar integration to three-dimensional integration by stacking drive circuits and memory cell arrays in different layers. Word line drive circuits are positioned in a first layer while memory cells are in a second layer above them, with bit line drive circuits in a third layer. This vertical arrangement increases integration density without proportionally increasing power consumption.

The drive circuits are segmented into separate functional blocks: word line drive circuits in the first layer and bit line drive circuits in the third layer. This segmentation allows independent optimization of each circuit block, enabling reduced transistor sizes and lower power consumption while maintaining stable write operations through coordinated control.

The patent applies different design optimizations to different parts of the system. In the drive circuits, transistor sizes are reduced for compactness, while in the memory cell layer, the magnetic tunnel junction elements are precisely engineered with specific tunnel barrier thicknesses and magnetic layer configurations to ensure stable write operations. This local optimization allows small transistors to coexist with reliable memory cell switching.

The patent introduces select gates as intermediary elements between the drive circuits and memory cells. These select gates act as buffers that amplify and condition the drive signals, ensuring that even with reduced transistor sizes in the drive circuits, the final write operations remain stable and reliable when applied to the memory cells.

The patent optimizes multiple parameters simultaneously: it reduces drive voltage to lower power consumption while compensating by adjusting magnetic tunnel junction parameters such as tunnel barrier thickness and magnetic layer composition. This allows the system to achieve low-power operation without sacrificing write capability, as the magnetic elements are engineered to switch at lower voltage thresholds.

The patent employs pulsed write operations where high current is applied briefly through the memory cells during write cycles. This periodic action allows sufficient write capability during the pulse duration while maintaining low average power consumption between pulses. The drive circuits are designed to deliver high peak currents only when needed for writing, rather than maintaining continuously high power levels.