Floating-Body MOSFET Memory Writing With Plate-Line Erase
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory devices using semiconductor elements face challenges in executing effective writing and refreshing operations, particularly due to issues like bit-line disturb during data transitions.
Innovation Solution
A memory device configuration with a plate line extending parallel to the word line and connected to the floating body of a MOSFET, allowing for new writing and refreshing operations through data latching and carrier injection/removal via sense amplifier circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a conventional 1T DRAM structure is used for high integration, then device density is improved, but bit-line disturb occurs during writing operations causing data instability
Solution Approach 1:
The patent divides the gate structure into two separate gates: a first gate (word line) and a second gate (plate line). This segmentation allows independent control of carrier injection and extraction operations, enabling selective writing to target cells while preventing disturb effects on non-selected cells. The first gate controls impact ionization for hole injection, while the second gate controls hole extraction, resolving the bit-line disturb problem in high-density 1T DRAM structures.
2Reliability
If negative potential is applied to non-selected word lines to prevent hole extraction, then data retention is improved, but writing operation complexity increases
Solution Approach 1:
The patent extracts the hole extraction function from the word line and assigns it to a dedicated plate line (second gate). This allows the word line to focus solely on selecting target cells and controlling impact ionization, while the plate line independently handles hole extraction for non-selected cells. This separation eliminates the need for complex negative potential control on non-selected word lines, simplifying the writing operation while maintaining data retention.
3Reliability
If plate electrode is set to high value for non-selective hole extraction, then bit-line disturb is reduced, but writing selectivity control becomes difficult
Solution Approach 1:
The patent implements coordinated control between the word line (first gate) and plate line (second gate) through feedback mechanisms. The word line selects target cells by controlling impact ionization, while the plate line responds by extracting holes from non-selected cells. This feedback-based coordinated control enables precise writing selectivity while maintaining reduced bit-line disturb, as the two gates work together to achieve selective data writing without affecting non-selected cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient and reliable writing and refreshing operations without the bit-line disturb issue, improving data stability and integrity in semiconductor memory devices.
Implementation Method 1
the plate line is connected to an electrode capacitively-coupled to a floating body of a MOSFET constituting a memory cell
Implementation Method 2
data stored in the memory cell belonging to the page is read and latched by a sense amplifier circuit
Implementation Method 3
holes, among holes and electrons generated by impact ionization within a channel due to electric current between the source and the drain
Implementation Method 4
causing the holes to flow into the body of the '0' data cell due to GIDL (gate induced drain leakage)
Data Source
AI summary
Provided is a semiconductor memory device that stores data by accumulating multiple carriers in an electrically floating body of a metal-oxide-semiconductor field-effect transistor. A plate line capacitively-coupled to the floating body is routed parallel to a word line in an isolated fashion for every word line so that, by applying voltage to the plate line, the multiple carriers are collectively erased along the word line. A writing operation of the semiconductor memory device is executed by causing sense amplifier circuits to read and latch data from cells along a selected word line, isolating bit lines from the sense amplifier circuits to erase data from the cells by applying voltage to the plate line belonging to the word line while simultaneously writing data into the sense amplifier circuits from the outside, and injecting multiple carriers into the bodies of the cells according to the states of the sense amplifier circuits.