Two-Time-Programmable Memory Cell via Source Drain Breakdown
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Solution Overview
Problem
One-time-programmable (OTP) devices in wireless telephones consume large die area and are prone to reliability failures due to variations in gate oxide breakdown locations, causing over-stressing of transistor regions during read operations.
Innovation Solution
A two-time-programmable (TTP) device is introduced, which creates separate conductivity paths between the gate and source and gate and drain of a programmable transistor, preventing breakdown at the channel region by controlling voltages, allowing for two logical states per cell without increasing die area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If OTP device uses gate oxide breakdown at channel region to store data, then data storage is achieved, but die area is large and reliability is poor
Solution Approach 1:
The patent segments the breakdown process into two distinct stages: first breakdown at the source region to form a conductivity path, and second breakdown at the drain region to form another conductivity path. This segmentation allows two logical states to be stored in a single transistor structure, reducing die area while improving reliability by avoiding channel region breakdown.
Solution Approach 2:
The patent transitions from a single-state storage model to a two-state storage model by utilizing different breakdown locations (source vs. drain regions). This dimensional expansion of the storage state space allows one transistor to represent two logical states, effectively reducing the die area requirement without sacrificing reliability.
2Ease of operation
If read voltage is applied to detect stored data after gate oxide breakdown, then data reading is enabled, but source and drain regions are over-stressed causing reliability failure
Solution Approach 1:
The patent introduces the well region as an intermediary element that mediates the voltage stress. By controlling the well voltage, the patent enables safe read operations at lower voltages without directly applying high stress to the source and drain regions, thus maintaining transistor reliability while enabling data reading.
Solution Approach 2:
The patent changes the voltage parameters dynamically during operation. During programming, high voltages are applied to create breakdowns at source/drain regions. During reading, the well voltage is controlled to enable low-voltage read operations, preventing over-stress of the transistor regions and maintaining reliability.
3Reliability
If gate oxide breakdown occurs at channel region, then current flow between gate and source/drain is enabled, but resistance varies with breakdown location affecting device performance
Solution Approach 1:
The patent applies local quality by creating breakdowns at specific locations (source and drain regions) rather than uniformly across the channel. By controlling the breakdown to occur at these localized regions, the patent ensures consistent resistance characteristics and improves device performance reliability, as the breakdown location is predetermined and controlled rather than random.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The TTP device reduces die area requirements and enhances reliability by allowing two logical states per cell, reducing the risk of transistor failure and improving read operations with lower read voltages.
Implementation Method 1
A gate oxide breakdown enables current flow between the transistor's gate and the transistor's source/drain region and the transistor's channel region when a read voltage is applied
Data Source
AI summary
A method includes selectively creating a first breakdown condition and a second breakdown condition at a semiconductor transistor structure. The first breakdown condition is between a source overlap region of the semiconductor transistor structure and a gate of the semiconductor transistor structure. The second breakdown condition is between ad rain overlap region of the semiconductor transistor structure and the gate.