Semiconductor Memory Redundancy Testing via Dynamic Address Latch
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Solution Overview
Problem
During the development phase of semiconductor memory apparatuses, testing for repairing defective memory cells is inefficient due to the need to support various redundancy fuse circuit structures and alternatives, making it unreasonable to develop for all forms, and without a redundancy fuse circuit, test evaluation of the redundancy repair function is not possible.
Innovation Solution
A semiconductor memory apparatus is designed with a memory control circuit, redundancy decoder, and redundancy address latch circuits that allow for efficient testing of defective memory cells by replacing specific memory cells with redundancy cells, using fuse circuits for non-volatile storage and switch circuits to selectively output redundancy addresses to the decoder, with priority control and sensor integration for optimal operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If various redundancy fuse circuit structures and alternatives are supported during development, then the redundancy repair function can be thoroughly tested, but the development cost and development period increase significantly
Solution Approach 1:
The test chip is designed with a universal test structure that can evaluate multiple types of redundancy circuits (fuse circuits, antifuse circuits, and non-fuse redundancy circuits) using a single integrated circuit. This allows comprehensive testing of redundancy repair functions without needing separate test chips for each redundancy type, thereby reducing development complexity while maintaining thorough testing capability.
2Productivity
If no redundancy fuse circuit is set, then development cost and period are reduced, but test evaluation of the redundancy repair function becomes impossible
Solution Approach 1:
A fuse circuit is introduced as an intermediary testing component that enables evaluation of redundancy repair functions during development without requiring the final product to include actual redundancy fuse circuits. The fuse circuit serves as a temporary testing mechanism that can be blown to simulate redundancy activation, allowing comprehensive testing while keeping the final product design flexible.
3Reliability
If physical redundancy fuse circuits are used, then non-volatile redundancy address storage is achieved, but the circuit structure becomes more complex and development is restricted
Solution Approach 1:
The test chip incorporates dynamic switching capability that allows the redundancy address storage to operate in different modes: fuse-based non-volatile storage for permanent defects, and non-fuse volatile storage for temporary testing. This dynamic configurability enables the same hardware to adapt to different testing scenarios and redundancy types, providing both non-volatile storage capability and structural flexibility.
Data Source
AI summary
A memory control circuit 10 controls an operation of reading stored data from a memory cell 50 connected to a word line WL and a bit line BL based on an address Address including a row address Ax and a column address Ay. When the address Address includes redundancy addresses P1 to P4 designating a word line WLa or a bit line BLc connected to a specific memory cell Cc, redundancy decoders 13-1 to 13-4 replace the specific memory cell Cc with a redundancy memory cell RCc connected to redundancy word lines RWL1 and RWL2 or redundancy bit lines RBL1 and RBL2. Redundancy address latch circuits 12-1 to 12-4 respectively hold the redundancy addresses P1 to P4, and erase the held redundancy addresses P1 to P4 based on a reset signal RS inputted from the memory control circuit 10.