Vertical Memory Array Structure for Self-Aligned Electrical Access
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Solution Overview
Problem
Current memory array technologies face challenges in efficiently forming vertically-stacked memory cells with reliable electrical access and lateral misalignment protection, particularly in the formation of NAND architecture and other non-volatile memory arrays.
Innovation Solution
The method involves forming a conductor tier on a substrate, creating a stack with alternating conductive and insulative tiers, using a metal halide to react with silicon and germanium to form sidewalls in trenches, and replacing sacrificial material with conductive material to form channel-material strings that extend through the tiers, ensuring electrical coupling and lateral alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically-stacked memory cells are formed using conventional methods, then memory density is increased, but lateral misalignment and electrical access reliability deteriorate
Solution Approach 1:
The patent forms sacrificial lines and sidewalls in advance before forming the final memory structure. The sacrificial lines are deposited and patterned first, then sidewalls are formed on them, creating a preliminary structure that guides subsequent processing steps and ensures precise lateral alignment of the vertically-stacked memory cells.
Solution Approach 2:
The patent introduces sacrificial lines as intermediary structures that facilitate the formation of vertically-stacked memory cells. These sacrificial lines serve as temporary placeholders and alignment references during fabrication, enabling precise positioning of memory cells while maintaining manufacturing feasibility. The sidewalls act as another intermediary element that protects and defines the boundaries of the sacrificial lines.
2Quantity of substance
If vertically-stacked memory cells are formed using conventional methods, then memory density is increased, but electrical access reliability deteriorates
Solution Approach 1:
The patent forms conductive material and electrical connections in advance through the sacrificial lines and sidewalls structure. This preliminary electrical infrastructure ensures that vertical electrical access paths are established before the final memory cell structure is complete, improving reliability by ensuring proper electrical coupling is achieved during the stacking process.
3Manufacturing precision
If complex fabrication processes are used to improve alignment, then manufacturing complexity increases
Solution Approach 1:
The patent employs self-aligned fabrication techniques where the sidewalls automatically form on the sacrificial lines through conformal deposition, and subsequent etching steps use the sidewalls as self-aligned masks. This self-service approach eliminates the need for additional alignment steps and complex lithography processes, achieving high lateral alignment precision while keeping the fabrication process relatively simple.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of memory arrays with reliable electrical access and improved lateral alignment, enhancing the performance and reliability of vertically-stacked memory cells in NAND architecture and other memory arrays.
Implementation Method 1
A metal halide is provided that reacts with the at least one of the silicon and germanium to form sidewalls of the lower horizontally-elongated trenches
Data Source
AI summary
A memory array comprising laterally-spaced memory blocks individually comprises a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The laterally-spaced memory blocks in a lower one of the conductive tiers comprises elemental-form metal that extends longitudinally-along the laterally-spaced memory blocks proximate laterally -outer sides of the laterally-spaced memory blocks. A metal silicide or a metal-germanium compound is directly against laterally-inner sides of the elemental-form metal in the lower conductive tier and that extends longitudinally-along the laterally-spaced memory blocks in the lower conductive tier. The metal of the metal silicide or of the metal-germanium compound is the same as that of the elemental-form metal. Other embodiments, including method, are disclosed.