3D Nonvolatile Memory Pad Layout for Noise-Resistant Biasing
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Solution Overview
Problem
3D nonvolatile memory devices face challenges in suppressing noise and are difficult to design and fabricate, leading to reliability issues.
Innovation Solution
A nonvolatile memory device design with a memory cell area vertically mounted on a peripheral circuit area, featuring a common source plate and multiple cell structures, and a peripheral circuit area with decoders and switches, including first and second metal pads for improved electrical connections, reducing noise and enhancing bias voltage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3D nonvolatile memory devices are fabricated to increase memory cells per unit lateral chip area, then storage capacity is improved, but device complexity and noise suppression difficulty increase
Solution Approach 1:
The patent transitions from 2D planar memory cell arrangement to 3D vertical stacking architecture. Cell structures are stacked vertically over the common source plate, with bit lines, word lines, and selection transistors arranged in multiple vertical layers. This dimensional change enables significantly higher memory cell density per unit lateral chip area while maintaining manufacturability through established 3D semiconductor fabrication processes.
Solution Approach 2:
The memory device is segmented into distinct functional regions: a memory cell area containing stacked cell structures, and a peripheral circuit area containing decoders and control circuits. The cell structures themselves are segmented into multiple vertical layers with separate bit lines, word lines, and selection transistors for each layer. This segmentation allows independent optimization and fabrication of different functional blocks, reducing overall device complexity.
2Quantity of substance
If 3D nonvolatile memory devices are fabricated to increase memory cells per unit lateral chip area, then storage capacity is improved, but noise suppression becomes more difficult
Solution Approach 1:
The patent extracts and separates noise-sensitive signal paths from noisy power and control lines through spatial segmentation. The memory cell area is physically separated from the peripheral circuit area, with dedicated contact structures and wiring paths connecting them. This extraction of sensitive functions from noisy environments reduces electromagnetic interference and signal noise in the 3D stacked architecture.
Solution Approach 2:
The patent introduces intermediate buffer structures and isolation layers between the memory cell array and peripheral circuits. Contact structures serve as intermediaries to connect the vertically stacked cell structures to the peripheral decoding circuits while providing electrical isolation. These intermediary elements mediate signal transmission and reduce noise coupling between densely packed 3D structures.
3Reliability
If multiple metal pads and contacts are added to enhance bias voltage capacity, then electrical connection reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple electrical connection functions into integrated contact structures. The first and second contacts extend from the common source plate to connect both the memory cell area and peripheral circuit area simultaneously. Multiple metal pads are combined into unified bonding structures that provide both mechanical support and electrical connectivity, reducing the number of discrete components while maintaining connection reliability.
Solution Approach 2:
The common source plate serves multiple functions: it acts as a mechanical substrate supporting the vertically stacked cell structures, provides electrical biasing to the memory cells, and serves as a reference ground plane for noise reduction. The metal pads provide both structural bonding surfaces and electrical connection points. This multi-functionality reduces the number of separate components needed, thereby reducing device complexity while enhancing reliability.
Data Source
AI summary
A nonvolatile memory device includes; a memory cell area including a common source plate, at least one cell structure under the common source plate, and a first metal pad under the at least one cell structure, and a peripheral circuit area on which the memory cell area is mounted, including a middle area , a first edge area, and a second metal pad on the first edge area. The memory cell area further includes a first contact extending from the common source plate and connected to the first metal pad. The peripheral circuit area further includes a second contact extending from a common source line switch and connected to the second metal pad. The first metal pad contacts with the second metal pad on the second metal pad.