Capacitorless DRAM Cell Layout for Capacitive Coupling Suppression
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Solution Overview
Problem
Capacitorless single-transistor DRAM memory cells face issues with large capacitive coupling between the word line and floating body, leading to data misreading or erroneous rewriting due to voltage swings during read or write operations, making it difficult to implement them practically.
Innovation Solution
A memory device structure with a semiconductor base material arranged vertically or horizontally, featuring impurity layers, gate insulating layers, and gate conductor layers, where the channel semiconductor layer is operated in saturation and linear regions to control voltage and form positive hole groups through impact ionization, with specific capacitance ratios and voltage settings to minimize capacitive coupling noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If capacitorless single-transistor DRAM memory cell is used, then packaging density is improved, but capacitive coupling noise between word line and floating body increases causing data misreading
Solution Approach 1:
The patent transitions from a planar two-dimensional memory cell layout to a three-dimensional vertical structure by erecting the semiconductor base material vertically on the substrate. This dimensional change allows the channel to extend in the vertical direction rather than horizontally, reducing the capacitive coupling area between the word line and floating body while maintaining high packaging density.
Solution Approach 2:
The patent divides the gate structure into multiple segments: a first gate insulating layer and second gate insulating layer surrounding the semiconductor base material at different vertical positions, with first and second gate conductor layers. This segmentation allows independent voltage control of different gate regions, enabling suppression of capacitive coupling noise while maintaining the capacitorless single-transistor structure.
2Ease of operation
If voltage is applied to word line during read operation, then data reading is enabled, but voltage swing transmits noise to floating body causing erroneous rewriting
Solution Approach 1:
The patent introduces an intermediary mechanism through the segmented gate structure where the first gate conductor layer acts as a mediator between the word line and the floating body. By controlling the voltage on the first gate conductor layer independently, the system can shield the floating body from voltage swings on the word line, preventing noise transmission while allowing data reading through the second gate conductor layer.
Solution Approach 2:
The patent applies preliminary anti-action by pre-setting the voltage on the first gate conductor layer to counteract the capacitive coupling effect before the word line voltage swing occurs. This preliminary voltage adjustment creates an opposing electric field that cancels out the noise transmission path, protecting the floating body from erroneous charging or discharging during read operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces capacitive coupling noise, ensuring a sufficient potential difference between logic states during writing and reading, thereby enhancing the reliability and practicality of capacitorless DRAM memory cells.
Implementation Method 1
an electron channel 107 extending from the source N+ layer 103 has a pinch-off point 108 and does not reach the drain N+ layer 104 connected with a bit line. If the MOS transistor 110 is operated with a gate voltage set to approximately 1⁄2 a drain voltage by applying high voltages to the bit line BL connected to the drain N+ layer and the word line WL connected to the gate conductive layer 105 as described above, electric field strength is maximized at the pinch-off point 108 in the vicinity of the drain N+ layer 104. As a result, accelerated electrons flowing from the source N+ layer 103 towards the drain N+ layer 104 collide with a Si lattice, and electron-hole pairs are created by kinetic energy lost at that moment (impact ionization phenomenon).
Data Source
AI summary
A memory device includes a page made up of plural memory cells arranged in a column on a substrate, and a page write operation is performed to hold positive hole groups generated by an impact ionization phenomenon, in a channel semiconductor layer by controlling voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region of each memory cell contained in the page and a page erase operation is performed to remove the positive hole groups out of the channel semiconductor layer by controlling voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region. The first impurity layer of the memory cell is connected with a source line, the second impurity layer is connected with a bit line, one of the first gate conductor layer and the second gate conductor layer is connected with a word line, and another is connected with a drive control line; during the write operation after the page erase operation, the positive hole group is formed in the channel semiconductor layer by an impact ionization phenomenon by controlling voltages applied to the word line, the drive control line, the source line, and the bit line; and an applied voltage/applied voltages of one or both of the word line and the drive control line is/are lowered with drops in a first threshold voltage of the first gate conductor layer and a second threshold voltage of the second gate conductor layer.