Semiconductor Fuse Programming via Dual I/O Interface
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Solution Overview
Problem
Semiconductor memory devices face challenges in programming fuses after encapsulation, as general fuses become inaccessible once encapsulated, limiting their ability to control internal operations effectively.
Innovation Solution
A semiconductor device with a first I/O part for buffering command/address signals to generate delay address signals and an internal address generator, along with a second I/O part using fuses that can be programmed according to logic levels of input data to control I/O characteristics, allowing for independent operation of memory blocks and flexible control of I/O characteristics during a test mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If general fuses are used to control internal operations, then the device can be programmed at wafer level, but the fuses become inaccessible and cannot be programmed after encapsulation
Solution Approach 1:
The device is divided into multiple independently operable memory blocks, each with its own fuse control capability. This segmentation allows different blocks to be programmed at different times and through different interfaces, making the system as a whole more flexible and accessible after encapsulation.
Solution Approach 2:
An additional I/O part is introduced as an intermediary interface that provides access to fuse programming capability after encapsulation. This intermediary I/O part allows external programming equipment to communicate with and program fuses through available external interfaces, bypassing the encapsulation barrier.
2Productivity
If multiple I/O lines are added to increase bandwidth, then performance improves, but device complexity increases
Solution Approach 1:
The additional I/O part is designed with multi-functionality, serving both as a data I/O interface for bandwidth expansion and as a fuse programming interface for configuration. This universal design allows the same physical interface to handle multiple tasks, reducing overall device complexity despite increased bandwidth capability.
Solution Approach 2:
The I/O parts are designed to operate independently and can be dynamically activated or deactivated based on operational mode. During normal operation, certain I/O parts handle data traffic while others remain inactive. During test/programming modes, different I/O parts are activated as needed, allowing flexible resource allocation without permanent complexity.
3Reliability
If memory blocks are made to operate independently without interference, then reliability improves, but control coordination becomes more difficult
Solution Approach 1:
The memory device is segmented into multiple independently controllable memory blocks, each with its own address space and control logic. This physical and logical segmentation ensures that operations in one block do not interfere with others, improving reliability while maintaining manageable control through modular architecture.
Solution Approach 2:
Not all I/O parts and memory blocks need to be active simultaneously. The system can activate only the necessary subset of blocks and I/O parts for each specific operation. This partial action approach reduces control coordination overhead while maintaining the independence and reliability benefits of the segmented architecture.
Data Source
AI summary
A semiconductor device includes a first input/output (I/O) part buffering command/address (C/A) signals inputted through a first pad part to generate delay address signals, an internal address generator generating a plurality of internal address signals according to a level combination of the delay address signals, and a second I/O part including a plurality of fuses selected by the plurality of internal address signals in a test mode. The plurality of fuses of the second I/O part are programmed according to logic levels of data inputted to the second I/O part through a second pad part to control I/O characteristics of the second I/O part.