3D Memory Cell Layout With Buried Bit Lines and Capacitors
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Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving high integration density and improved electric characteristics while maintaining operation speed and yield as they are scaled down.
Innovation Solution
A semiconductor memory device design incorporating a data storage layer, an interconnection layer, and a selection element layer with specific configurations, including bit lines, word lines, and capacitors, which are sequentially stacked to enhance integration density and electric characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor devices are scaled down to increase integration density, then integration density is improved, but operation speed and yield deteriorate
Solution Approach 1:
The patent transitions from planar 2D transistor channels to 3D vertically-stacked channels extending in the depth direction. Multiple channel regions are formed above the substrate, allowing integration density to increase while maintaining adequate channel control and electrical performance through the vertical dimension.
Solution Approach 2:
The patent implements a nested structure where bit line contact plugs are formed within trenches, surrounded by bit lines, which are in turn surrounded by insulating layers. This nested arrangement allows compact integration while maintaining electrical isolation and signal integrity.
2Ease of manufacture
If conventional planar structures are used, then fabrication is simpler, but integration density and electric characteristics are limited
Solution Approach 1:
The patent divides the transistor structure into multiple segmented channel regions formed at different vertical levels. Each channel region can be independently controlled by its own gate structure, allowing complex functionality to be achieved through modular segmentation while using standard semiconductor fabrication techniques.
Solution Approach 2:
The invention adds the vertical dimension to the traditional planar structure, creating multi-layer channel regions that extend upward from the substrate. This vertical stacking enables higher integration density without requiring fundamentally new fabrication processes, as the channels are formed using conventional epitaxial growth and patterning methods.
3Ease of operation
If capacitors and bit lines are left exposed, then connectivity is simpler, but device complexity and fabrication difficulty increase
Solution Approach 1:
The patent performs preliminary actions by forming bit line contact plugs and embedding bit lines within insulating layers before forming the channel structures. This preliminary placement and encapsulation of interconnect elements simplifies subsequent fabrication steps and reduces the overall device complexity.
Solution Approach 2:
The patent introduces insulating layers as intermediary structures that encapsulate bit lines and provide controlled interfaces between different device components. These intermediary layers facilitate connectivity while managing electrical isolation and mechanical stress, reducing fabrication difficulty.
Data Source
AI summary
A semiconductor memory device is disclosed. The semiconductor memory device may include a data storage layer including data storage devices, an interconnection layer disposed on the data storage layer, and a selection element layer provided between the data storage layer and the interconnection layer. The interconnection layer may include bit lines extending in a first direction. The selection element layer may include a cell transistor connected between one of the data storage devices and one of the bit lines, and the cell transistor may include an active pattern and a word line, which crosses the active pattern and is extended in a second direction crossing the first direction.