3D Memory Capacitor Structure for High Capacitance With Lower Leakage
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Solution Overview
Problem
The challenge in semiconductor memory devices is to increase capacitance while avoiding excessive leakage current, which is difficult due to the limitations of etching and film plating capabilities when reducing the thickness of the dielectric material layer.
Innovation Solution
A capacitor structure is formed with a first capacitor structure having columnar lower electrodes and a second capacitor structure with U-shaped lower electrodes, both with dielectric layers and upper electrodes that fill gaps, effectively increasing the surface area and reducing the requirements for etching and film plating.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the thickness of the dielectric material layer is decreased to increase capacitance, then the capacitance increases, but the leakage current becomes excessive
Solution Approach 1:
The patent transitions from a planar capacitor structure to a three-dimensional structure with vertical electrodes extending into the substrate. This dimensional change increases the effective surface area of the dielectric layer without reducing its thickness, thereby increasing capacitance while avoiding excessive leakage current that would result from thinning the dielectric layer.
Solution Approach 2:
The patent embeds vertical electrodes within the substrate, nesting the capacitor structure inside the existing substrate volume. This allows the dielectric layer to extend vertically through multiple levels, increasing the effective surface area and capacitance without requiring a reduction in dielectric thickness, thus avoiding leakage current issues.
2Quantity of substance
If a very deep channel is etched on the substrate to accommodate the capacitor structure, then the capacitance requirements are met, but the etching capability requirements increase significantly
Solution Approach 1:
Instead of etching extremely deep horizontal channels, the patent creates vertical electrode structures that extend upward from the substrate surface. This dimensional reorientation transforms the manufacturing challenge from deep horizontal etching to more manageable vertical structure formation, reducing etching capability requirements while still achieving the necessary capacitance.
3Manufacturing precision
If upper and lower electrode plates and dielectric film are plated evenly onto the substrate surface, then the capacitor structure is formed, but the film plating capability requirements increase
Solution Approach 1:
The patent forms dielectric and electrode structures in the vertical dimension rather than relying solely on horizontal planar plating. This allows for more relaxed film plating requirements since the critical dimensions are controlled vertically through deposition thickness rather than requiring perfect uniformity across large horizontal areas.
Data Source
AI summary
The present application relates to a capacitor device and a manufacturing method thereof, and a memory. forming a first capacitor structure on a substrate, includes: a first capacitor dielectric layer, a first upper electrode, a plurality of first lower electrodes arranged at intervals; the first capacitor dielectric layer at least covers sidewalls of the first lower electrodes, and the first upper electrode fills up gaps at an outer side of the first capacitor dielectric layer; forming a second capacitor structure on the first capacitor structure, the second capacitor structure includes a second capacitor dielectric layer, a second upper electrode, and a plurality of second lower electrodes arranged at intervals; the second lower electrodes are of a U-shaped structure, bottoms of the second lower electrodes are in contact with tops of the first lower electrodes, the second capacitor dielectric layer is at least located on surfaces of the second lower electrodes.