3D Memory Carrier Substrate Removal for Source Layer Formation
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Solution Overview
Problem
The degradation of CMOS devices due to collateral thermal cycling and hydrogen diffusion during the manufacture of three-dimensional memory devices poses challenges for the performance of support circuitry in vertical NAND strings, limiting the effectiveness of existing technologies.
Innovation Solution
The method involves forming a three-dimensional memory device by replacing a carrier substrate with a source layer and contact structures, using an alternating stack of insulating and electrically conductive layers, and physically exposing the distal end of vertical semiconductor channels to create a source layer directly on the channels, thereby enhancing support circuitry performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a carrier substrate is used during manufacturing, then the memory structure can be formed and supported, but the support circuitry performance degrades due to thermal cycling and hydrogen diffusion
Solution Approach 1:
The patent removes the carrier substrate from the final memory device structure. The carrier substrate is used only during manufacturing to support the formation of memory structures, then it is completely removed. This extraction eliminates the source of thermal cycling and hydrogen diffusion damage that would otherwise affect the support circuitry performance during device operation.
Solution Approach 2:
The patent forms the complete memory structure including source regions, channels, and gates on the carrier substrate before removal. All critical components are preliminarily formed and positioned while the carrier provides mechanical support, then the carrier is removed to prevent subsequent damage from thermal and chemical exposure.
2Reliability
If the carrier substrate is removed to improve support circuitry performance, then thermal and hydrogen damage is reduced, but additional manufacturing steps are required
Solution Approach 1:
The carrier substrate is completely removed from the structure after serving its manufacturing purpose. This extraction eliminates the need for ongoing thermal and chemical management during device operation, improving support circuitry performance despite adding a removal step to manufacturing.
Solution Approach 2:
The carrier substrate is discarded after its manufacturing function is complete. It serves as a temporary platform for forming memory structures, then is removed entirely. This approach converts a potentially harmful permanent component into a useful temporary tool that is discarded when no longer needed.
3Reliability
If source layer is formed directly on vertical semiconductor channels, then contact resistance is reduced and performance is improved, but precise positioning and formation is more difficult
Solution Approach 1:
The source layer is formed preliminarily on the carrier substrate surface before carrier removal. This preliminary formation allows precise positioning relative to the vertical channels, then the carrier is removed to achieve direct contact with minimal resistance. The preliminary action on the stable carrier substrate enables precision that would be difficult to achieve otherwise.
Solution Approach 2:
The carrier substrate acts as an intermediary during source layer formation. It provides a stable platform for forming the source layer with precise positioning, then is removed to allow direct contact between the source layer and vertical channels. The intermediary enables precise formation without compromising final contact quality.
Data Source
AI summary
A three-dimensional memory device may include an alternating stack of insulating layers and spacer material layers formed over a carrier substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory stack structures are formed through the alternating stack. Each memory stack structure includes a respective vertical semiconductor channel and a respective memory film. Drain regions and bit lines can be formed over the memory stack structures to provide a memory die. The memory die can be bonded to a logic die containing peripheral circuitry for supporting operations of memory cells within the memory die. A distal end of each of the vertical semiconductor channels is physically exposed by removing the carrier substrate. A source layer is formed directly on the distal end each of the vertical semiconductor channels. A bonding pad can be formed on the source layer.