3D Memory Cell Structure That Avoids High-Aspect-Ratio Etching
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Solution Overview
Problem
Current semiconductor memory technologies face challenges in achieving high-density memory devices with efficient manufacturing processes, particularly in forming transistors with gate electrodes and source/drain electrodes in three-dimensional memory arrays, which often require complex and high-aspect-ratio etching processes that can be costly and inefficient.
Innovation Solution
A method for manufacturing a 3D memory array involving the formation of trench openings in a multilayered structure, where a ferroelectric layer acts as a gate dielectric, and conductive pillars are formed as source/drain electrodes with kink portions covered by a semiconductor layer, allowing for the avoidance of high-aspect-ratio etching and increased process margin through the use of isolation structures and selective etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If high aspect ratio etching is used to form memory cells, then vertical integration is achieved, but process margins are reduced and manufacturing precision deteriorates
Solution Approach 1:
The etching process is divided into two separate operations: first forming trench openings, then forming electrode openings. This segmentation avoids the need for a single high aspect ratio etching step, thereby improving process margins while achieving the required vertical integration.
Solution Approach 2:
The trench openings are formed in advance before the electrode openings. This preliminary action allows the subsequent electrode formation to occur in pre-prepared structures with more favorable aspect ratios, improving manufacturing precision.
2Shape
If high aspect ratio etching is used to form memory cells, then 3D structure is achieved, but device complexity increases
Solution Approach 1:
The complex 3D structure is achieved through segmented etching steps rather than a single complex high aspect ratio etch. This divides the manufacturing complexity into manageable stages with better process control.
Solution Approach 2:
The patent uses planar patterning techniques to define the 3D structure, transitioning from vertical etching challenges to lateral patterning that is more controllable and less complex.
3Ease of manufacture
If conventional etching methods are used, then manufacturing process is simpler, but memory density decreases
Solution Approach 1:
By segmenting the etching process into two simpler steps rather than one complex step, the patent maintains ease of manufacture while achieving higher memory density through improved process control and better structure definition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of high-density memory devices with improved reliability and reduced complexity in the manufacturing process, enhancing the electrical performance and scalability of memory cells by minimizing cross-talk between transistors and optimizing electrode formation.
Implementation Method 1
a semiconductor layer is disposed alongside the gate layer and the first isolation structure and between the source electrode and the drain electrode, wherein the semiconductor layer laterally covers the kink portions of the source electrode and the drain electrode
Data Source
AI summary
A 3D memory array including multiple memory cells and a method of manufacturing the same are provided. Each memory cell includes a first isolation structure, source and drain electrodes, a gate layer, a channel layer and a memory layer. The source and drain electrodes are disposed on opposite sides of the first isolation structure, and the source and drain electrodes comprise kink portions. The gate layer is disposed beside the source and drain electrodes and the first isolation structure. The channel layer is disposed between the gate layer and the source electrode, the first isolation structure and the drain electrode, and the channel layer extends between the source and drain electrodes and covers the kink portions of the source and drain electrodes. The memory layer is disposed between the gate layer and the channel layer and extends beside the gate layer and extends beyond the channel layer.