3D Vertical Memory Cell Layout for Density and Cell Isolation
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Solution Overview
Problem
Current memory devices face challenges in increasing memory cell density, reducing power consumption, and lowering manufacturing costs, particularly in three-dimensional vertical architectures.
Innovation Solution
The development of a 3D vertical self-selecting memory array with a compacted memory cell design, featuring conductive contacts and insulative materials arranged in a specific geometric pattern, where storage elements are recessed in arch-shaped configurations to reduce contact area and enhance cell isolation, allowing for higher density and controlled cell dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell density is increased through 3D vertical architecture, then storage capacity improves, but manufacturing complexity and cost increase
Solution Approach 1:
The memory array is divided into multiple decks stacked vertically, with each deck containing memory cells formed by intersections of word lines and digit lines. This segmentation allows independent processing and formation of each deck, simplifying the manufacturing process while achieving high density through vertical stacking.
Solution Approach 2:
The patent transitions from 2D planar memory architecture to 3D vertical architecture by stacking multiple decks of memory cells vertically. This dimensional change increases storage capacity per unit area while maintaining manufacturability through standardized vertical stacking processes.
2Quantity of substance
If memory cell dimensions are reduced to increase density, then storage capacity improves, but cell isolation and voltage application become difficult
Solution Approach 1:
Storage elements are formed in recesses within the conductive layers, creating a nested structure where the storage element is embedded in the word line/digit line intersections. This nesting provides natural isolation and maintains electrical integrity even as cell dimensions are reduced.
Solution Approach 2:
The patent introduces arch-shaped conductive structures with varying thickness profiles, where the thickness is locally optimized to provide adequate voltage application at critical regions while maintaining small overall cell dimensions. The arch shape concentrates electrical field where needed for reliable cell operation.
3Manufacturing precision
If contact area between storage element and conductive material is reduced, then cell isolation improves, but electrical connection reliability may deteriorate
Solution Approach 1:
The conductive structures are formed with arch-shaped curved profiles rather than straight vertical walls. This curvature optimizes the electrical field distribution and contact area with the storage element, providing reliable electrical connection while maintaining compact cell isolation. The arch shape naturally concentrates the electrical field at the contact points.
Data Source
AI summary
Methods for, apparatuses with, and vertical 3D memory devices are described. A vertical 3D memory device may comprise: a plurality of contacts associated with a plurality of digit lines and extending through a substrate; a plurality of word line plates separated from one another by respective dielectric layers and including a first plurality of word line plates and a second plurality of word line plates; a dielectric material positioned between the first plurality and the second plurality of word line plates, the dielectric material extending in a serpentine shape over the substrate; a plurality of pillars formed over and coupled with the plurality of contacts; and a plurality of storage elements each comprising chalcogenide material positioned in a recess between a respective word line plate and a respective pillar, wherein the recess is of an arch-shape, and the chalcogenide material in the recess contacts the respective word line plate.