3D Charge-Storage Memory Cell Layout for Higher Density
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Solution Overview
Problem
As semiconductor devices continue to reduce minimum feature sizes for increased integration density, challenges arise in efficiently forming and patterning material layers to create high-density memory devices.
Innovation Solution
A method involving the formation of a multi-layer stack with alternating dielectric and sacrificial layers, followed by patterning and replacement with conductive layers, and the creation of vertically stacked memory cells using a field effect transistor (FET) architecture, allowing for higher cell density and 2 bits per cell storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The memory device is divided into multiple stacked layers including bit lines, source lines, charge storage nodes, and tunnel dielectric layers. Each layer is formed through separate deposition and patterning steps, allowing independent optimization of each component while achieving high overall integration density.
Solution Approach 2:
The patent transitions from planar 2D memory architecture to three-dimensional stacked architecture. Multiple bit line sets and source line sets are stacked vertically above the substrate, enabling significant increase in storage capacity per unit area while managing the complexity through vertical integration rather than horizontal expansion.
2Quantity of substance
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but feature size reduction creates additional fabrication challenges
Solution Approach 1:
Mandrel structures are formed first as templates before depositing the tunnel dielectric layer and charge storage node materials. This preliminary patterning step establishes precise feature locations and dimensions that guide subsequent fabrication steps, ensuring consistent feature sizes even at reduced dimensions.
Solution Approach 2:
Tunnel dielectric layers are deposited as intermediary structures between the conductive bit/source lines and the charge storage nodes. These dielectric layers with controlled thickness (e.g., 5-20 nm) serve as precise spacers that define feature dimensions and ensure uniform spacing in the stacked architecture.
3Quantity of substance
If vertically stacked memory cells are implemented to increase cell density, then storage capacity per unit area increases, but device structure and manufacturing processes become more complex
Solution Approach 1:
Multiple functional structures are nested within each other vertically. Bit lines and source lines from different memory cell layers are stacked and interconnected through via structures. Charge storage nodes are positioned between tunnel dielectric layers that are themselves between conductive line layers, creating a nested arrangement that maximizes space utilization.
Solution Approach 2:
The stacked architecture uses shared structures across multiple memory cells. For example, a single bit line set can serve multiple memory cells in different layers, and source lines are shared among adjacent cells. This multi-functionality reduces the total number of required components while maintaining high cell density.
Data Source
AI summary
A memory device includes a multi-layer stack disposed on a substrate and including conductive layers and dielectric layers stacked alternately, a channel layer penetrating through the conductive layers and the dielectric layers, a charge storage layer disposed between the conductive layers and the channel layer, an insulating layer penetrating through the conductive layers and the dielectric layers and disposed between the charge storage layer and the multi-layer stack, and a first conductive pillar and a second conductive pillar enclosed by the channel layer.