3D Memory Cell Plug Structure Without Sacrificial Layer Removal
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Solution Overview
Problem
The increasing integration level in memory devices complicates the process of removing sacrificial layers and filling areas with conductive material in 3D memory structures, leading to manufacturing difficulties.
Innovation Solution
A memory device design that alternately stacks insulating layers and conductive gate lines, forming a cell plug with a blocking layer, charge trap layer, tunnel insulating layer, and channel layer, and etching these layers together to form a vertical hole, thereby simplifying the manufacturing process by eliminating the need to remove sacrificial layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If sacrificial layers are used to form 3D memory structures, then the manufacturing process can achieve complex 3D configurations, but the process complexity and difficulty of removing sacrificial layers increases
Solution Approach 1:
The patent extracts and eliminates the sacrificial layer component from the manufacturing process. Instead of depositing sacrificial layers and then removing them, the invention directly forms the gate line structure without requiring sacrificial materials, thereby simplifying the process and removing the problematic removal step entirely
Solution Approach 2:
The patent inverts the conventional approach by not using sacrificial layers at all. Rather than following the traditional path of depositing sacrificial material and then removing it, the invention directly forms the final gate line structure through alternative deposition and etching methods, effectively taking the opposite route to achieve the same 3D structure
2Ease of manufacture
If sacrificial layers are removed and areas are filled with conductive material, then gate lines can be formed, but the process steps increase and defect risk increases
Solution Approach 1:
The patent merges the gate line formation process with the insulating layer formation process. By depositing conductive material directly over insulating layers and performing selective etching, the invention combines multiple process steps into a unified approach, eliminating the separate sacrificial layer deposition and removal steps
Solution Approach 2:
The patent performs preliminary actions by pre-defining the gate line patterns through selective deposition of conductive materials before final structure formation. The conductive materials are strategically placed and etched in advance to create the desired gate line configurations, simplifying subsequent processing steps
Data Source
AI summary
Provided herein may be a memory device and a method of manufacturing the same. The memory device may include a plurality of insulating layers and a plurality of gate lines configured to be alternately stacked, and a cell plug configured to pass through the plurality of insulating layers and the plurality of gate lines, wherein the plurality of gate lines, each made of a conductive material, are etched together with the plurality of insulating layers, and the cell plug includes a blocking layer, a charge trap layer, a tunnel insulating layer, a channel layer, and a core pillar.