3D Electro-Chemical Memory Cell for Multi-Level Signal Storage
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Solution Overview
Problem
Existing electro-chemical memory devices face challenges in increasing memory cell density while effectively storing multi-level signal information due to limitations in ion exchange and resistance state manipulation.
Innovation Solution
A memory cell design incorporating an electro-chemical memory element with a control element, featuring a source line, bit line, storage channel layer, electrolyte layer, ion reservoir layer, and floating gate electrode layer, along with a control channel structure, control source line, and control gate dielectric layer, allows for three-dimensional stacking and multi-level signal storage through controlled ion movement and conductance variation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of the electro-chemical memory device is reduced to increase memory cell density, then memory cell density is improved, but the ability to effectively store multi-level signal information deteriorates
Solution Approach 1:
The patent transitions from two-dimensional planar structure to three-dimensional vertical stacking by positioning the storage channel layer, electrolyte layer, ion reservoir layer, and floating gate electrode layer in stacked layers. This vertical arrangement increases storage capacity per unit area while preserving the ion exchange mechanism necessary for multi-level signal storage.
Solution Approach 2:
The patent implements nested layering where the storage channel layer is positioned between source and bit lines, the electrolyte layer is disposed on the storage channel layer, the ion reservoir layer is disposed on the electrolyte layer, and the floating gate electrode layer is disposed on the ion reservoir layer. Each layer is nested within the vertical structure to maximize space utilization while maintaining functional integrity for multi-level signal storage.
2Ease of manufacture
If conventional two-dimensional planar structure is used, then manufacturing is simpler, but memory cell density is limited
Solution Approach 1:
The patent adopts a three-dimensional vertical stacking architecture where functional layers are arranged perpendicular to the substrate surface. This approach achieves high memory cell density by utilizing the vertical dimension while maintaining compatibility with standard semiconductor manufacturing processes through sequential layer deposition.
Solution Approach 2:
The memory device is segmented into distinct functional layers: storage channel layer for ion reception, electrolyte layer for ion transport, ion reservoir layer for ion supply, and floating gate electrode layer for signal storage. Each layer is independently formed and optimized, enabling modular manufacturing while achieving high density through vertical integration.
3Reliability
If ion receiving layer concentration is increased to improve signal storage, then electrical resistance decreases, but control over multi-level signal states becomes difficult
Solution Approach 1:
The electrolyte layer serves as an intermediary between the ion reservoir layer and the storage channel layer, enabling controlled ion transport. By regulating ion flow through the electrolyte layer, the system can precisely modulate the ion concentration in the storage channel layer, thereby controlling the electrical resistance to achieve multiple stable states for multi-level signal storage.
Solution Approach 2:
The patent utilizes changes in ion concentration as a controllable parameter to modulate the electrical resistance of the storage channel layer. By adjusting the amount of ions transferred from the ion reservoir through the electrolyte to the storage channel, the system can achieve multiple distinct resistance states corresponding to different signal levels, enabling reliable multi-level storage with controllable operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enables efficient three-dimensional integration of memory cells, enabling multi-level signal storage and arithmetic operations by varying channel conductance based on applied write voltages, facilitating advanced computing-in-memory devices.
Implementation Method 1
The electro-chemical memory device allows ions to be exchanged between the ion receiving layer and the ion supply layer under an external stimulus
Implementation Method 2
an electro-chemical memory element with a control element, featuring a source line, bit line, storage channel layer, electrolyte layer, ion reservoir layer, and floating gate electrode layer
Implementation Method 3
The electro-chemical memory device uses the electrical resistance properties of the ion receiving layer, which changes depending on the concentration of the ions contained in the ion receiving layer, to store signal information
Data Source
AI summary
A semiconductor device includes an electro-chemical memory element and a control element electrically connected to each other. The electro-chemical memory element includes a source line disposed on a plane, a bit line disposed to be spaced apart from the source line and extending in a vertical direction, a storage channel layer disposed to be connected to the source line and the bit line on the plane, an electrolyte layer disposed on the storage channel layer, an ion reservoir layer disposed on the electrolyte layer, and a floating gate electrode layer disposed on the ion reservoir layer. The control element includes a control channel structure disposed on the floating gate electrode layer, a control source line disposed on the control channel structure, a control gate dielectric layer disposed on a side surface of the control channel structure, and a control word line disposed on the control gate dielectric layer.