3D Memory Cell Structure Integrating Source and Bit Lines

Solution Overview

Problem

Conventional 3D flash memory devices face challenges in space utilization and complex fabrication processes due to the difficulty in interconnecting source and bit lines, leading to inefficient use of space and increased fabrication steps.

Innovation Solution

A semiconductor device design where the coupling region between the source line and bit line is integrated within the cell string structure, allowing for increased space utilization and reduced fabrication steps by forming channel regions over the semiconductor substrate and using an oxide-nitride-oxide dielectric layer for charge storage, with the source line extending parallel to the memory cell structure and the bit line perpendicular to it.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If a pipe gate structure is used to form 3D memory cells, then memory cells can be stacked vertically, but additional space is required to connect source and bit lines to upper metal lines, deteriorating space utilization

Engineering Contradiction:

Core Design Contradiction:

Length of moving objectVSArea of stationary object

Solution Approach 1:

The source line and bit line are merged within the cell string structure itself. The source line is formed as part of the cell string, and the bit line is formed to contact the channel region within the same vertical structure, eliminating the need for separate connection spaces outside the cell string.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The source line and bit line connections are nested within the cell string structure. The source line is embedded in the cell string, and the bit line contacts are integrated into the same vertical column, allowing the connection functions to be contained within the memory cell footprint.

Inventive Principle:

Principle #7Nested doll (Nesting)

2Length of moving object

If a pipe-channel-shaped 3D memory cell structure is used, then memory cells can be formed vertically, but the fabrication process becomes highly complex

Engineering Contradiction:

Core Design Contradiction:

Length of moving objectVSDevice complexity

Solution Approach 1:

The fabrication process is segmented into distinct stages: forming the cell string structure, forming the source line, forming the bit line, and forming the charge storage layer. Each stage uses standard semiconductor processes that can be independently optimized and controlled.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Instead of forming the pipe gate structure first and then adding connections, the invention forms the cell string structure and integrates the source and bit lines as part of the same fabrication sequence, reversing the conventional approach of separate connection formation.

Inventive Principle:

Principle #13The other way round (Inversion)

Data Source

PatentUS9478559B2Semiconductor device and method of fabricating the same

Publication Date: 2016.10.25

AI summary

A semiconductor device and a method of fabricating the same are disclosed. The semiconductor device includes: a memory cell structure formed over a semiconductor substrate; a channel portion formed in the semiconductor substrate; a through-hole formed to pass through the memory cell structure; a first channel region formed over sidewalls of the through-hole; and a second channel region formed at a center part of the through-hole, and spaced apart from the first channel region, wherein each of the first channel region and the second channel region is coupled to the channel portion.