Solid-State Devices TRIZ Cases

A metallic carrier layer integrates a compensating layer to mechanically stabilize semiconductor components without added height.

A semiconductor fabrication method trims hard mask patterns to control critical dimensions in peripheral regions.

Sandwiched photosensitive layer detects reflected light to identify fingerprint patterns, reducing apparatus thickness by eliminating bulky optical components.

Merges source and bit line connections inside the vertical memory cell structure, eliminating extra space for interconnects and reducing fabrication steps.

Optimizing indium tin zinc atomic ratios improves charge mobility and etch uniformity, resolving manufacturing cost and reliability trade-offs.

Semiconductor pressure sensors with bias voltage applying circuits resolve signal detection versus integration difficulty in touch display panels.

Compiler selects configurable hardware options in deep learning accelerators to reduce energy consumption and computation time.

A pixel structure uses a crossed interconnection pattern to electrically link multiple light-emitting diode elements for precise alignment.

Integrated sensing electrodes and thin film transistors reduce border width while maintaining high touch detection accuracy.

Replacing polymer insulators with an anodized film on a metal plate lowers costs while improving thermal conductivity.

An Au-based eutectic alloy bonding layer with a recessed bent portion prevents moisture absorption and manages thermal stress for high-output LED chips.

A tantalum oxide layer with controlled oxygen content changes electrical resistance to store data in nonvolatile memory elements.

Replacing mechanical elements with piezoelectric materials reduces device thickness while maintaining force touch sensing capability.

Melted glass surfaces bond semiconductor components to carriers, eliminating organic adhesives that degrade under heat and light exposure.

A display panel uses film layers with decreasing refractive indexes to direct light rays toward the exit surface.

A transparent conductive oxide layer prevents silver ion reduction during etching, blocking particle defects and external pollution to enhance OLED reliability.

A reverse-biased diode blocks electric current flow into the LDMOS substrate.

Varying thin-film transistor channel dimensions adjusts blue and white pixel voltages to reduce side yellowish phenomena caused by refractive anisotropy.

Diborane decomposes into a boron nucleation layer that reduces tungsten precursors, eliminating voids in high aspect ratio features.

Depositing polymer layers on the wafer eliminates separate infrared filters, reducing device complexity and manufacturing costs.

Vertical stacking of multiple variable resistance layers boosts storage capacity while avoiding manufacturing complexity from shrinking device dimensions.

Surrounding gate electrodes around a shared silicon pillar reduce deposition time and enhance integration density.

Vertical semiconductor channels use stressor pillars to induce tensile stress and boost charge carrier mobility.

Segmenting the semiconductor layer into poly-Si and a-Si regions suppresses leak current during the OFF state, enhancing display reliability.

Shared bit and word lines connect memory cells across multiple dice, reducing resistance and capacitance while lowering latency.

Depositing organic semiconductor layers onto curved substrates to integrate active circuits into ophthalmic devices without increasing manufacturing complexity.

A flexible temperature sensor uses a mixed fluid of ionic liquid and porous conductive particles to detect heat on curved surfaces.

Supplementary exposure and baking of photoresist bank layers suppresses heat-caused loosening, preserving aperture ratio and functional layer uniformity.

Conductive vias and a doped epitaxial layer form diode junctions, eliminating coordinated double-side photolithography for CMOS compatibility.

Relocating driving circuits to a separate board eliminates non-display regions at panel edges, resolving image discontinuities in large displays.

An inclined channel geometry reduces disconnection risks in lower regions while minimizing thickness to boost data processing capacity.

Annealing oxide semiconductor thin film transistors above 100°C stabilizes channel layers against plasma damage during manufacturing.

Resistant layers distribute electrical current across nanostructures to prevent localized damage and enhance device longevity.

A protective layer coats the common electrode line end portion to prevent damage during patterning.

A memory transistor uses a high work function gate electrode to reduce electron emission from the gate.

A memory device structure merges horizontal and vertical cell orientations to increase storage density.

Integrated test registers in the base chip enable independent micro bump testing, removing reliance on external controllers.

Modulating surface Fermi energy defines pixels in a focal plane array, eliminating deep trench etching and reducing surface leakage current.

A step-shaped contact electrode links the cathode and auxiliary electrode in an organic light emitting display device.

PEDOT polyanion composition limits acidity using specific stabilizers, preventing adjacent layer degradation in optoelectronic devices.

Metal-free organic molecules improve OLED efficiency and stability by removing metal ions while maintaining high photoluminescence quantum yields.

Vertically stacked cell pillars surround a dummy pattern region with a damp-proof structure to protect the semiconductor device.

Segmenting signal lines across gate and interlayer insulation films prevents scratches from glass particles during scribing, maintaining display reliability.

Conductive substrate with patterned insulation directs light emission and moves heat away, resolving poor thermal management in luminous devices.

Composite nitride phosphors replace unstable oxide materials to resolve thermal degradation and moisture sensitivity while maintaining high luminous efficiency.

A semiconductor component with a monolithically integrated coil reduces electromagnetic interference by merging the coil directly into the substrate.

Segmenting the substrate into rigid areas and a flexible bending zone reduces dead space while preserving structural integrity and reliable wiring.

Atomic layer deposition uses chlorine-free precursors to form ferroelectric layers in memory devices.

A nested epitaxial structure confines compressive stress in the channel region, resolving strain delivery challenges during semiconductor scaling.

A transparent conductive film on a semiconductor layer is patterned using photo-resist masks to define electrode areas.

Combining anode and bank formation into a single mask process reduces defect rates and boosts production yield.

Tapered grooves under 45 degrees separate adjacent pixels to suppress leakage current from SRH generation while maintaining high sensitivity.

Narrow bandgap non-fullerene acceptors extend spectral coverage beyond 850 nm to resolve limited near-infrared absorption in organic photovoltaic devices.

An intermediary dopant layer reduces operating voltage and off-currents in organic transistors by mediating charge injection between electrodes and the channel.

Selective epitaxial growth forms semiconductor cores around nanowire channels to boost carrier mobility.

Oxide-to-oxide bonding stacks single crystal LED layers in a 3D micro display, reducing thermal expansion mismatches and defects.

Source degeneration inductors steer electrostatic discharge current through clamp circuits, reducing peak gate-to-source voltage to prevent oxide rupture.

An error correction circuit accumulates amplifier output current on a feedback capacitor to cancel charge injection and noise errors.

An elastomeric enclosure absorbs mechanical shock energy to protect portable radiographic detector components from drops.

Pixelated detectors apply data consistency metrics to identify noisy pixels, correcting malfunctioning elements without replacing the entire array.

Light-obstructing layer defines pixels via permeable regions, eliminating the pixel definition layer to resolve manufacturing complexity and mixed colors.

Wafer-level processing embeds passives in glass via dry etching and reflow, resolving electrical isolation failures at high frequencies.

Shared interlayer dielectric reduces manufacturing complexity while enabling high-k metal gate logic and charge storage NVM structures.

A hollow waveguide structure with a conductor pin penetrating an opening to connect conductors.

Selective etching using a sacrificial oxide layer creates dual-depth shallow trench isolation with one mask, reducing manufacturing time and process complexity.

A light-emitting diode structure uses a high-reflectivity layer covering electrode extensions to redirect emitted light outward.

A cross-point storage device applies specific voltage relationships to memory cells to ensure accurate selection.

A semiconductor device structure on a SeOI substrate uses a back control gate region to modulate threshold voltage and effective channel width.

A light blocking portion shields a photo sensor from direct organic light emitting diode radiation within an organic light emitting display apparatus.

Segmented gate lines with asymmetric widths place transistors on wider sections, resolving the trade-off between manufacturing cost and reduced pixel area.

Fire-polishing thin glasses with refractive index above 1.60 reduces surface roughness while maintaining high transparency and chemical resistance.

A single polysilicon layer memory cell uses Fowler-Nordheim tunneling for charge transfer.

Simultaneous formation of gate and blocking dielectric layers reduces mask sets and preserves channel dopant profiles.

Traps capture siloxane and silicon dioxide before deposition degrades combustion sensor performance.

Solid-phase epitaxial growth forms monocrystalline silicon layers on insulating films, suppressing short channel effects in 50 nm memory devices.

Restricting column spacer movement via a storage hole reduces substrate shifting and light leakage while maintaining uniform cell gap stability.

Merging N-type and P-type transistor regions into shared contact holes reduces pixel area, enabling high-definition liquid crystal displays.

Polyimide masks with metal oxide layers enable electrostatic induction to eliminate shadow defects and improve yield.

Array substrate fan-out lines use dual conductive layers and variable contact distances to stabilize electrical resistance.

Ferrite layer shields RF signals from metal interference, enabling seamless dual interface communication.

A memory device selects distinct optimal read voltages for inner and outer pillar strings using a dedicated determination unit.

Alternating transition metal oxide and leakage control layers form a varistor layer that reduces electrical conductivity.

Vertically stacked semiconductor pillars connect to electrode films through insulating layers for dense memory cell integration.

Dual-layer etching protects sensitive passivation films from chemical degradation while maintaining manufacturing efficiency.

Loading a low melting point metal ball onto a short solder bump allows laser heating to melt the ball, adjusting the height without damaging the conductor pad.

Removing the semiconductor substrate from a middle layer simplifies via formation while enabling global shutter operation and high dynamic range functionality.

Half-tone masks selectively etch ion induction layers, reducing TFT substrate manufacturing from nine to six masks.

Staggered multi-layer transparent electrodes increase electric field strength to improve liquid crystal rotation and display quality metrics.

Heated grippers and chucks keep adhesive above glass transition to prevent warpage during debonding.

A three-dimensional non-volatile NOR flash memory device stacks field-effect transistors vertically to achieve high storage density.

A bipolar junction transistor structure integrates a heating element on its emitter to drive phase change material cells.

A lensless optical navigation device directs laser radiation via total internal reflection surfaces to capture fingerprint ridge periods.

A planar substrate design integrates electrical busbars and optical structures in a single layer to simplify manufacturing.

Oblique illumination generates scattered light captured by an offset sensor array to produce high contrast image frames.

A gallium nitride light emitting device uses a fluorescent layer to convert blue excitation into stable red emission.

A vertical junction field-effect transistor driver uses a U-shaped epitaxial channel to boost conductance and lower voltage drop.

Dual common electrodes sandwich a pixel electrode to form parallel capacitors, restoring storage capacitance lost during high-resolution scaling.

Lateral insulation prevents parasitic capacitances and corrosion at bond pads, maintaining measuring accuracy during eutectic bonding.

A dual-gate nitride semiconductor device modulates carrier concentration via hole injection to enable normally-off operation.