Amplifier ESD Protection via Source Inductor and Clamp Circuit
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Solution Overview
Problem
Amplifiers fabricated with sub-micron CMOS processes are susceptible to electro-static discharge (ESD) due to their small physical dimensions, leading to potential failure, and existing ESD protection circuitries are inadequate in handling fast ESD current pulses, which can cause gate oxide rupture in NMOS transistors.
Innovation Solution
An amplifier design incorporating a clamp circuit with a series of diodes between the gate and source of an NMOS transistor, coupled with a source degeneration inductor, to steer ESD current through the inductor, reducing the voltage drop across the transistor and preventing gate oxide rupture, while using faster diodes to enhance turn-on speed and minimize capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If sub-micron CMOS processes are used to fabricate amplifiers, then cost is reduced and integration is improved, but the transistors become more susceptible to ESD damage due to small physical dimensions
Solution Approach 1:
The patent introduces a clamp circuit as an intermediary protective layer between the ESD source and the vulnerable transistor gate oxide. This clamp circuit, positioned at the input pad, acts as a mediator that intercepts and limits voltage spikes before they can reach and damage the transistor gate, thus protecting the vulnerable sub-micron transistor while maintaining the benefits of sub-micron fabrication
Solution Approach 2:
The clamp circuit is designed to activate preemptively when voltage thresholds are approached, conducting ESD current away from the transistor gate before the gate oxide can be damaged. This preliminary protective action occurs at the input pad level, preventing the harmful ESD pulse from reaching the vulnerable transistor in the first place
2Reliability
If conventional ESD protection circuitries are used, then some ESD protection is provided, but they are inadequate in handling fast ESD current pulses, causing gate oxide rupture
Solution Approach 1:
The patent changes the electrical parameters of the protection circuit by using a clamp circuit with specifically selected diode characteristics that enable ultra-fast response times. The clamp circuit is designed to respond to ESD pulses with rise times in the picosecond range, much faster than conventional protection circuits, thereby preventing gate oxide rupture even during fast ESD current pulses
Solution Approach 2:
The ESD protection function is segmented into multiple protective elements: the clamp circuit at the input pad, the inductor in the source path, and the transistor itself. This segmentation allows each element to handle specific aspects of ESD protection, with the clamp circuit specifically optimized to handle the initial fast voltage spike and prevent gate oxide damage
3Reliability
If a clamp circuit with series diodes is used to protect against ESD, then gate oxide rupture is prevented, but amplifier performance may be impacted
Solution Approach 1:
The clamp circuit is designed with local quality optimization by using small-sized diodes that provide the necessary ESD protection only at the critical input pad interface. The diodes are sized and positioned to provide protection exactly where needed without adding excessive capacitance or resistance that would degrade the overall amplifier performance across the operating bandwidth
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed ESD protection circuit effectively reduces the peak Vgs voltage across the NMOS transistor, preventing gate oxide rupture and ensuring reliable operation under ESD conditions without significantly impacting amplifier performance.
Implementation Method 1
the clamp circuit is arranged to conduct current from the inductor to the gate and from the gate to the inductor when a large voltage pulse is applied to the pad, to provide electro-static discharge, ESD, protection for the transistor
Implementation Method 2
an inductor coupled to a source of the transistor... conduct current from the inductor to the gate and from the gate to the inductor
Data Source
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AI summary
An amplifier (e.g., an LNA) with improved ESD protection circuitry is described. In one exemplary design, the amplifier includes a transistor (410), an inductor (412), and a clamp circuit (422). The transistor (410) has a gate coupled to a pad (450) and provides signal amplification for the amplifier. The inductor (412) is coupled to a source of the transistor (410) and provides source degeneration for the transistor (410). The clamp circuit (422) is coupled between the gate and source of the transistor (410) and provides ESD protection for the transistor (410). The clamp circuit (422) may include al least one diode coupled between the gale and source of the transistor (410). The clamp circuit (422) conducts current through the inductor (412) to generate a voltage drop across the inductor (412) when a large voltage pulse is applied to the pad (450). The gate-to-source voltage (Vgs) of the transistor (410) is reduced by the voltage drop across the inductor (412), which may improve the reliability of the transistor (410).