Stacked Memory Self-Testing via Integrated Test Registers
Solution Overview
Problem
Current 3D semiconductor devices require external controllers for normal and test operations, limiting their ability to perform self-testing and micro bump characteristic testing independently.
Innovation Solution
A stacked memory device comprising a core chip and a base chip with integrated data receivers, test registers, compression circuits, and address registers that allow for normal and test operations without external controller intervention, utilizing separate normal and test ports for data and control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a stacked memory device uses external controllers for normal and test operations, then the device structure remains simple, but the device cannot perform self-testing and micro bump characteristic testing independently
Solution Approach 1:
The base chip is equipped with a data receiver, test register, compression circuit, and address register that enable the stacked memory device to perform self-testing operations independently without requiring external controller intervention. The test mode circuit activates these components to allow the device to test itself autonomously.
2Adaptability or versatility
If separate normal and test ports are implemented in the base chip, then operational flexibility and reliability are enhanced, but device complexity increases
Solution Approach 1:
The base chip is divided into distinct functional components: a data receiver for normal operations, a test register for test operations, a compression circuit for data compression, and an address register for address management. Separate normal and test ports are implemented to allow independent access to these functions, enabling operational flexibility while maintaining clear functional separation.
Data Source
AI summary
A stack memory device may include a core chip and a base chip. The core chip may include a data receiver, a strobe signal generation unit, and a test register. The data receiver may be configured for receiving data outputted from the core chip through a first normal port. The strobe signal generation unit may be configured to generate a data strobe signal based on one of a normal strobe signal and a test strobe signal depending on an operation mode. The test register may store data outputted from the data receiver in response to the data strobe signal.