Stressed Vertical Semiconductor Channels for 3D NAND Scaling
Solution Overview
Problem
Three-dimensional memory devices face challenges in enhancing charge carrier mobility and on-current for vertically scaled NAND strings due to the increasing length of vertical semiconductor channels, which affects the performance and stacking capacity of these devices.
Innovation Solution
The implementation of stressed vertical semiconductor channels using a stressor pillar structure with a dielectric metal oxide material, silicon nitride, or thermal silicon oxide, applied with a stressor material that induces vertical tensile stress, and the use of sacrificial layers to generate lateral compressive stress, which enhances charge carrier mobility and on-current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical semiconductor channels are scaled to increase stacking capacity, then the number of word lines that can be stacked increases, but charge carrier mobility and on-current deteriorate due to increasing channel length
Solution Approach 1:
The patent applies stressor materials with different lattice constants than the semiconductor channel material to induce mechanical stress. By changing the physical parameter of stress state in the channel, charge carrier mobility is enhanced despite increased channel length from vertical scaling. The stressor material lattice constant mismatch creates tensile or compressive stress that modifies carrier transport properties.
Solution Approach 2:
The patent uses composite structures combining semiconductor channel materials with stressor materials having different lattice constants. This composite approach allows the stressor material to mechanically influence the semiconductor channel, improving charge carrier mobility through stress-induced effects while maintaining the vertical scaled architecture.
2Quantity of substance
If vertical semiconductor channels are scaled to increase stacking capacity, then the number of word lines that can be stacked increases, but on-current deteriorates due to increasing channel length
Solution Approach 1:
The patent modifies the stress state parameter in the semiconductor channel by introducing stressor materials. This parameter change compensates for the increased channel length effect, maintaining on-current levels despite vertical scaling that increases the number of stackable word lines.
Solution Approach 2:
The stressor material acts as an intermediary that transfers mechanical stress to the semiconductor channel. This intermediary structure enables indirect control of charge carrier transport properties without directly altering the channel geometry or material composition, thereby maintaining on-current during vertical scaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves charge carrier mobility and on-current in vertical semiconductor channels, enabling the vertical scaling of three-dimensional memory devices and increasing the number of word lines that can be stacked, thereby enhancing the performance and capacity of the memory devices.
Implementation Method 1
The stressor pillar structure applies a vertical tensile stress to the vertical semiconductor channels
Implementation Method 2
The lateral compressive stress applied to the memory stack structure is provided by: forming backside recesses by removing the sacrificial material layers and depositing a compressive-stress-generating conductive material within the backside recesses
Data Source
AI summary
Three-dimensional memory devices include structures that induce a vertical tensile stress in vertical semiconductor channels to enhance charge carrier mobility. Vertical tensile stress may be induced by a laterally compressive stress applied by stressor pillar structure. The stressor pillar structures can include a stressor material such as a dielectric metal oxide material, silicon nitride, thermal silicon oxide or a semiconductor material having a greater lattice constant than that of the channel. Vertical tensile stress may be induced by a compressive stress applied by electrically conductive layers that laterally surround the vertical semiconductor channel, or by a stress memorization technique that captures a compressive stress from sacrificial material layers. Vertical tensile stress can be generated by a source-level pinning layer that prevents vertical expansion of the vertical semiconductor channel. Vertical tensile stress can be induced by using a layer stack including polysilicon and a silicon-germanium alloy for the vertical semiconductor channel.