3D Stacked NAND Memory Pillars and Electrode Integration
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Solution Overview
Problem
The miniaturization of planar structures in NAND flash memories is approaching its limits due to technological limitations and increasing costs, necessitating the development of vertically stacked memory cells to reduce bit cost effectively.
Innovation Solution
A semiconductor memory device is designed with vertically stacked semiconductor pillars, multiple electrode films, and insulating films, featuring a three-dimensional memory cell configuration and a method for manufacturing that includes forming memory trenches and slits to integrate memory cells and control gate electrodes, allowing for efficient interconnect pulling out with fewer process steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar structure miniaturization is continued, then memory capacity increases, but processing technology limitations and lithography device costs increase
Solution Approach 1:
The patent transitions from planar (2D) memory structure to vertically stacked (3D) memory structure. Memory cells are arranged in multiple layers along the vertical direction, with semiconductor pillars extending through insulating films and electrode films stacked in different layers. This dimensional change allows increased memory capacity without requiring further miniaturization of planar features, thereby avoiding the limitations of processing technology and lithography device costs.
2Quantity of substance
If vertically stacked memory cells are implemented, then bit cost is reduced, but manufacturing process complexity increases
Solution Approach 1:
The manufacturing process is divided into distinct stages: forming memory trenches, forming semiconductor pillars, forming insulating films, forming electrode films, and forming control gate electrodes. Each stage is independently optimized and can be performed using existing semiconductor manufacturing techniques. The segmented approach allows complex 3D structures to be built incrementally, reducing overall manufacturing complexity while achieving bit cost reduction through increased storage density.
Solution Approach 2:
The patent employs preliminary actions in the manufacturing process, such as forming placeholder structures (memory trenches and initial insulating layers) before building the final 3D memory cell structure. Control gate electrodes are formed in advance and positioned to extend over multiple memory cell layers, simplifying subsequent assembly steps. These preliminary structures guide the formation of the final stacked configuration, making the overall manufacturing process more manageable.
3Quantity of substance
If three-dimensional memory cell configuration is used, then integration density increases, but interconnect formation complexity increases
Solution Approach 1:
The control gate electrodes serve multiple functions: they control memory cells in multiple layers simultaneously and also serve as interconnect structures. The electrode films are formed to extend in both the vertical direction (through insulating films to reach semiconductor pillars in different layers) and the horizontal direction (to connect with bit lines and source lines). This multi-functionality reduces the need for separate interconnect structures, simplifying the overall interconnect formation process while maintaining high integration density.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a substrate, semiconductor pillars, first electrode films, a second electrode film, a first insulating film, a second insulating film, and a contact. The semiconductor pillars are provided on the substrate, extend in a first direction crossing an upper surface of the substrate, and are arranged along second and third directions being parallel to the upper surface and crossing each other. The first electrode films extend in the third direction. The second electrode film is provided between the semiconductor pillars and the first electrode films. The first insulating film is provided between the semiconductor pillars and the second electrode film. The second insulating film is provided between the second electrode film and the first electrode films. The contact is provided at a position on the third direction of the semiconductor pillars and is connected to the first electrode films.