Wafer-Level Embedding of Passive Elements in Glass Substrates
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Solution Overview
Problem
Current methods for embedding passive elements in glass substrates are complex, costly, and limited by 2D planar characteristics, leading to inefficient electrical isolation and high-frequency failures, while traditional silicon substrate methods face complications in seed layer deposition and electroplating processes.
Innovation Solution
A wafer-level manufacturing method involving dry-etching a highly-doped silicon wafer to form a mould, anodic bonding with a glass wafer, reflowing the glass to fill cavities, and using the silicon wafer as a seed layer for copper electroplating to embed passive elements in a glass substrate, simplifying the process and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional surface processing technology is used to prepare RF passive elements, then the manufacturing process is simple, but the component performance is limited due to 2D planar characteristics and the electrical path is short
Solution Approach 1:
The patent transitions from 2D planar surface processing to 3D volumetric manufacturing by embedding passive elements within the bulk of the glass substrate. This is achieved through wafer-level processing with through-glass vias and three-dimensional electrode structures, enabling extended electrical paths and improved component performance while maintaining manufacturing efficiency through batch processing capabilities
2Reliability
If 3D interconnection is implemented by layer-to-layer stacking with adapter plates, then the electrical path is extended, but the manufacturing process becomes complicated and costs increase
Solution Approach 1:
The patent merges multiple separate manufacturing steps into a unified wafer-level processing approach. Through-glass vias, passive element formation, and electrode patterning are all performed in an integrated sequence on full wafers before dicing, eliminating the need for separate adapter plates and layer-by-layer assembly operations
Solution Approach 2:
The patent performs preliminary wafer-level processing of all critical features (via formation, passive elements, electrodes) before final substrate separation. This preliminary bulk processing on complete wafers simplifies subsequent assembly by providing pre-configured modules that require no further complex manufacturing steps
3Device complexity
If silicon substrate with TSV process is used, then the manufacturing process is simplified compared to stacking, but the process control becomes complicated and expensive due to seed layer deposition and electroplating requirements
Solution Approach 1:
The patent changes the material parameter from conductive silicon to insulating glass as the substrate, which fundamentally alters the manufacturing approach. This eliminates the need for TSV electroplating and seed layer deposition, replacing them with glass-compatible via formation and filling techniques that are simpler to control and less expensive to implement
Solution Approach 2:
The patent replaces expensive, complex electroplating processes with more economical glass processing techniques. The glass substrate itself serves as the final structure without requiring additional metallic interconnection layers, eliminating costly electroplating steps while maintaining electrical functionality through glass-filled vias and printed electrodes
4Device complexity
If silicon substrate is used for embedding passive elements, then the manufacturing process is simplified, but electrical isolation fails at high frequencies due to conductive properties and nano-size constraints of dielectric barrier layer
Solution Approach 1:
The patent inverts the conventional approach by using an insulating glass substrate instead of a conductive silicon substrate. This fundamental material inversion naturally provides electrical isolation without requiring thin dielectric barrier layers, as the glass matrix itself is an excellent insulator that maintains isolation performance at high frequencies
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the creation of high-precision, compact, and reliable 3D passive elements with improved electrical isolation and thermal stability, reducing production time and costs, and allowing for self-separating glass substrates with embedded passive elements.
Implementation Method 1
anodically-bonding a glass wafer to the highly-doped silicon mould wafer obtained in step 1 in a vacuum
Implementation Method 2
heating the bonded wafers obtained in step 2 in air at a temperature higher than the softening point temperature of the glass, maintaining the temperature until the molten glass is reflowed to fill gaps
Implementation Method 3
dry-etching the passive component structure mould of highly-doped silicon embedded in the glass substrate
Implementation Method 4
filling, via copper electroplating, the blind holes in the glass substrate after the passive component structure mould has been etched
Data Source
AI summary
A wafer-level manufacturing method for embedding a passive element in a glass substrate is disclosed. A highly-doped silicon wafer is dry etched to form a highly-doped silicon mold wafer, containing highly-doped silicon passive component structures mold seated in cavity arrays; a glass wafer is anodically bonded to the highly-doped silicon mold wafer in vacuum pressure to seal the cavity arrays; the bonded wafers are heated so that the glass melts and fills gaps in the cavity arrays, annealing and cooling are performed, and a reflowed wafer is formed; the upper glass substrate of the reflowed wafer is grinded and polished to expose the highly-doped silicon passives; the passive component structure mold embedded in the glass substrate is fully etched; the blind holes formed in the glass substrates after the passive component structure mold has been etched is filled with copper by electroplating; the highly-doped silicon substrate and unetched silicon between the cavity arrays are etched, and several glass substrates embedded with a passive element are obtained; to form electrodes for the passives, a metal adhesion layer is deposited, and a metal conductive layer is electroplated. The process is simple, costs are low, and the prepared passive elements have superior performance.