Memory Transistor with High Work Function Gate and ONO Stack
Solution Overview
Problem
Conventional non-volatile semiconductor memory transistors suffer from poor data retention and limited transistor lifetime due to leakage currents through insulating layers, and existing processes for forming memory transistors are often incompatible with those used for logic transistors in integrated circuits.
Innovation Solution
A non-volatile memory transistor with an oxide-nitride-oxide (ONO) dielectric stack and a high work function gate electrode formed from doped polysilicon, which includes a multi-layer charge storage layer with a trap-free bottom oxynitride and a charge-trapping top oxynitride layer, enhancing data retention and compatibility with logic transistors on a common substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a silicon-rich charge trapping layer is used, then the initial program-erase window is large, but the data retention time is poor with rapid window collapse
Solution Approach 1:
The charge trapping layer is divided into multiple discrete layers (first charge trapping layer, second charge trapping layer, third charge trapping layer) with different materials and properties. Each layer serves specific functions: the first layer (Si-rich) provides high initial window, the second layer (SiO2) acts as a barrier to reduce leakage, and the third layer (Si-rich) provides additional charge storage. This segmentation resolves the contradiction by distributing functions across layers rather than relying on a single layer.
Solution Approach 2:
The charge trapping structure uses a composite of multiple materials including silicon-rich oxynitride, silicon dioxide, and silicon nitride in specific configurations. This composite structure combines the advantages of each material: Si-rich layers for charge storage capacity and SiO2 layers for leakage reduction, achieving both large initial window and improved data retention.
2Duration of action of stationary object
If a high quality nitride layer with low Si concentration is used, then the data retention is improved, but the initial program-erase window is reduced
Solution Approach 1:
Instead of using a single uniform nitride layer, the structure segments the charge trapping function across multiple layers with different compositions. The SiO2 second charge trapping layer specifically addresses leakage issues for improved retention, while the Si-rich first and third layers maintain the initial program-erase window.
Solution Approach 2:
Different regions of the charge trapping structure have different material compositions optimized for different functions. The Si-rich regions (first and third layers) provide high charge storage capacity for large initial window, while the SiO2 region (second layer) provides low leakage for improved data retention. This local quality differentiation resolves the contradiction.
3Ease of manufacture
If conventional memory transistor processes are used, then memory transistors can be formed, but they are incompatible with logic transistor fabrication processes
Solution Approach 1:
The memory transistor structure is designed to be formed using standard CMOS fabrication processes that are also used for logic transistors. The multi-layer charge trapping structure can be integrated into existing CMOS process flows without requiring separate specialized processes, enabling both memory and logic devices to be fabricated on the same substrate using universal processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly improves data retention and extends the operating life of memory transistors while enabling the integration of both memory and logic transistors on a common substrate, enhancing the efficiency of semiconductor device fabrication.
Implementation Method 1
A non-volatile memory transistor with an oxide-nitride-oxide (ONO) dielectric stack and a high work function gate electrode formed from doped polysilicon
Implementation Method 2
a high work function gate electrode formed from doped polysilicon
Data Source
AI summary
A semiconductor device includes an oxide-nitride-oxide (ONO) dielectric stack on a surface of a substrate, and a high work function gate electrode formed over a surface of the ONO dielectric stack. The ONO dielectric stack includes a multi-layer charge storage layer including a silicon-rich, oxygen-lean top silicon nitride layer and an oxygen-rich bottom silicon nitride layer. The high work function gate electrode includes a P+ doped polysilicon layer.