3D Semiconductor Memory With Damp-Proof Dummy Structure
Solution Overview
Problem
Two-dimensional semiconductor memory devices have limited integration density due to the high cost of equipment required for forming fine patterns, making it challenging to achieve both high performance and low cost, and three-dimensional devices require cost-effective manufacturing processes to overcome these limitations.
Innovation Solution
A semiconductor device with a substrate featuring a cell array region and a dummy pattern region, including vertically extending cell active pillars with alternately stacked cell gate patterns and interlayer insulating patterns, and a damp-proof structure surrounding the cell array region to reduce manufacturing costs and prevent contamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two-dimensional semiconductor memory devices are used to achieve fine patterns, then manufacturing precision is improved, but device complexity and manufacturing cost increase due to high-cost equipment requirements
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cell layers are stacked in the vertical direction, allowing fine patterns to be formed in the horizontal plane using conventional lithography while achieving high integration density through vertical stacking. This resolves the contradiction by maintaining manufacturing precision requirements at a manageable level while avoiding the need for extremely high-cost hyper-fine patterning equipment.
Solution Approach 2:
The memory device is divided into multiple identical memory cell layers stacked vertically. Each layer contains word lines, bit lines, and memory elements arranged in a standardized configuration. This segmentation into repeatable modular units allows conventional manufacturing equipment to produce each layer with standard precision, while the overall device achieves high integration through the stacked architecture.
2Productivity
If three-dimensional semiconductor memory devices are formed to increase integration density, then productivity is improved, but manufacturing reliability deteriorates due to process complexity
Solution Approach 1:
The patent forms all necessary structures for multiple memory cell layers simultaneously in a single lithography and etching process cycle. Word lines, bit lines, and memory element structures are patterned and formed for the entire stack before any subsequent processing. This preliminary formation of complete layer structures ensures consistent alignment and reduces the cumulative effect of process variations, thereby maintaining manufacturing reliability while achieving high integration density.
Solution Approach 2:
The memory device uses universal structures that serve multiple functions across different layers. Word lines and bit lines are formed with consistent dimensions and materials throughout the stack, and the same etching and deposition processes are applied to all layers. This universality simplifies the manufacturing process and improves reliability by reducing the number of unique process steps that could introduce variations or defects.
3Reliability
If dummy patterns are added to surround the cell array region to prevent contamination, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent combines the dummy pattern structures with the actual memory cell structures in the same vertical stack. The dummy word lines and dummy bit lines are integrated into the existing layer structure, sharing the same insulating layers and conductive material layers as the functional cells. This merging approach provides contamination prevention through the dummy patterns while avoiding additional structural complexity, as the dummy and functional structures are formed together in a unified architecture.
Data Source
AI summary
A semiconductor device has a substrate that includes a cell array region and a dummy pattern region surrounding the cell array region. The cell array region includes a cell structure having a plurality of cell active pillars extending in a vertical direction from the cell array region of the substrate and includes cell gate patterns and cell gate interlayer insulating patterns alternately stacked on the substrate. The cell gate patterns and cell gate interlayer insulating patterns have sides facing the cell active pillars. The dummy pattern region includes a damp-proof structure.