Replacement Gate Transistor and NVM Integration via Interlayer Dielectric
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Solution Overview
Problem
There is a need to enhance the performance of integrated circuits that combine non-volatile memory (NVM) and logic functions while minimizing cost increases, particularly in the context of replacement gate technology, which aims to improve performance by using a high-k dielectric and metal gate without sacrificing logic performance.
Innovation Solution
The integration of a replacement gate transistor and a non-volatile memory cell involves forming a charge storage layer and a dummy gate in both NVM and logic portions, using an interlayer dielectric that is removed from the NVM portion but retained in the logic portion, and replacing the dummy gate with a high-k dielectric and metal gate structure to optimize performance and cost efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If replacement gate technique is used to enhance logic performance with high-k dielectric and metal gate, then logic performance is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent merges the formation of replacement gate transistor and non-volatile memory cell into a single integrated process. The interlayer dielectric serves dual purposes: as part of the replacement gate structure in logic regions and as the tunnel dielectric for charge storage in NVM regions. This consolidation reduces manufacturing steps and complexity while achieving both logic performance enhancement and NVM functionality.
Solution Approach 2:
The interlayer dielectric material performs multiple functions across different device regions. In logic portions, it forms part of the high-k dielectric stack for enhanced transistor performance. In NVM portions, it serves as the tunnel dielectric layer for charge storage. This multi-functionality reduces the need for separate processing steps and materials, thereby reducing manufacturing complexity and cost.
2Reliability
If replacement gate technique is used to achieve high performance NVM and logic, then performance is improved, but manufacturing cost increases
Solution Approach 1:
The patent combines the formation of high-performance logic transistors and NVM cells into a single integrated manufacturing process. By using the same interlayer dielectric material and processing steps for both device types, the patent eliminates redundant manufacturing steps and reduces overall production cost while maintaining high performance for both logic and NVM functions.
Solution Approach 2:
The interlayer dielectric serves universal purposes across different device architectures. The same material deposition and processing steps create the appropriate dielectric structure for both replacement gate logic transistors (where it forms part of the gate dielectric stack) and NVM cells (where it forms the tunnel dielectric). This universality reduces manufacturing cost by eliminating the need for separate processing lines or additional materials.
3Reliability
If interlayer dielectric is removed from NVM portion but retained in logic portion, then NVM functionality is enabled, but additional processing steps are required
Solution Approach 1:
The patent applies local quality by having the interlayer dielectric present in logic regions but removed in NVM regions. This spatial differentiation allows the same initial material deposition to serve different functions: forming part of the gate dielectric in logic devices while creating the tunnel dielectric structure in NVM devices. The selective removal is achieved through region-specific processing that targets only the NVM portions, enabling NVM functionality without compromising logic device performance.
Solution Approach 2:
The interlayer dielectric is deposited in advance as part of the common processing sequence for both logic and NVM devices. In NVM regions, this preliminary deposition creates the tunnel dielectric structure that will be used later for charge storage. The dielectric is then selectively removed from NVM regions in a subsequent step, but its early formation as part of the standard process sequence reduces the need for entirely separate NVM-specific processing steps.
Data Source
AI summary
A first dielectric layer is formed over a semiconductor layer in an NVM region and a logic region. A charge storage layer is formed over the first dielectric layer in the NVM and logic regions. The charge storage layer is patterned to form a dummy gate in the logic region and a charge storage structure in the NVM region. A second dielectric layer is formed over the semiconductor layer in the NVM and logic regions which surrounds the charge storage structure and the dummy gate. The dummy gate is replaced with a logic gate. The second dielectric layer is removed from the NVM region while protecting the second dielectric layer in the logic region. A third dielectric layer is formed over the charge storage structure, and a control gate layer is formed over the third dielectric layer.