Fan-out Line Resistance Variation in Array Substrates

The patent applies different structural configurations to different regions of the fan-out lines. Specifically, signal lines in the center region have different resistance characteristics compared to those at the edges. The patent adjusts the number of conductive layers, contact configurations, and line widths locally across the fan-out portion to compensate for resistance variations, allowing each region to have optimized electrical properties despite the reduced peripheral area.

The patent systematically varies multiple parameters across the fan-out portion including the number of conductive layers (first and second conductive layers), contact dimensions and positions, line widths, and spacing between signal lines. These parameter changes are designed to maintain uniform resistance characteristics across all fan-out lines regardless of their position, thereby compensating for the effects of reduced peripheral area.

The patent implements region-specific design variations within the fan-out portion. Center signal lines and edge signal lines are designed with different structural parameters including varying numbers of conductive layers, different contact configurations, and adjusted line widths. This local differentiation allows each region to be optimized for its specific electrical requirements, maintaining overall resistance uniformity despite the compacted fan-out area.

The patent employs asymmetric design strategies where the structural parameters of fan-out lines are not uniform across all positions. Specifically, signal lines at different locations have intentionally different configurations (number of layers, contact positions, line widths) to compensate for the non-uniform electrical paths created by the reduced fan-out area, thereby achieving symmetric electrical performance outcomes.