Varistor Layer Snake Current Prevention
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Solution Overview
Problem
Highly integrated semiconductor memory devices face issues with snake currents, which can cause memory cells to malfunction, especially in three-dimensionally stacked configurations.
Innovation Solution
A method involving the formation of a varistor layer with a transition metal oxide layer and a leakage control layer on a substrate, where the transition metal oxide layer contains an excessive amount of transition metal, and the leakage control layer is alternately stacked with the transition metal oxide layer to reduce leakage currents, thereby preventing snake currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cells are three-dimensionally stacked to increase integration density, then productivity and integration density are improved, but snake current increases causing memory cells to malfunction
Solution Approach 1:
The bit line is divided into multiple independent bit line segments by inserting isolation patterns between adjacent memory cell strings. This segmentation prevents snake current from flowing continuously through non-selected memory cells, thereby maintaining reliability in three-dimensionally stacked configurations while preserving high integration density.
Solution Approach 2:
Isolation patterns are introduced as intermediary structures between adjacent memory cell strings connected to the same bit line. These isolation patterns act as mediators that block snake current flow while allowing normal bit line operation, enabling reliable three-dimensional stacking without compromising integration density.
2Ease of manufacture
If conventional manufacturing processes are used for simple structures, then ease of manufacture is maintained, but manufacturing precision deteriorates for complex three-dimensional structures
Solution Approach 1:
Isolation patterns are formed in advance during the bit line formation process before memory cell string fabrication. This preliminary action ensures precise alignment of isolation patterns with bit lines and enables subsequent three-dimensional stacking operations to proceed with high manufacturing precision while maintaining process simplicity.
Solution Approach 2:
The formation of isolation patterns is merged with the existing bit line formation process flow. By combining these functions into a unified process sequence, the patent achieves high manufacturing precision for complex three-dimensional structures without significantly increasing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces leakage currents when the varistor is turned off, preventing malfunction and enhancing the performance of non-volatile memory devices by acting as a switching device that does not generate snake currents.
Implementation Method 1
The transition metal oxide layer is formed to contain an excessive transition metal compared to its stable state
Data Source
AI summary
Provided is a method of manufacturing a semiconductor device having a switching device capable of preventing a snake current. First, a transition metal oxide layer and a leakage control layer are alternately stacked on a substrate 1 to 20 times to form a varistor layer. The transition metal oxide layer is formed to contain an excessive transition metal compared to its stable state. The leakage control layer may be formed of one selected from the group consisting of a Mg layer, a Ta layer, an Al layer, a Zr layer, a Hf layer, a polysilicon layer, a conductive carbon group layer, and a Nb layer.