Vertical JFET Driver for Memristor Array Switching
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Solution Overview
Problem
Existing memristor array designs face challenges in providing sufficient switching voltage and current while minimizing the planar area footprint, particularly in deep learning neural network processors, due to the need for high-resistance and low-resistance state separation in multiple state cells.
Innovation Solution
A vertical junction field-effect transistor (JFET) driver device with a U-shaped epitaxial channel wrapping around a vertical gate region is used, providing a longer channel width without increasing the planar surface area, enabling high conductance and reduced voltage drop for efficient memristor switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If planar transistors are used to drive memristor arrays, then sufficient switching voltage and current can be provided, but the planar area footprint increases significantly
Solution Approach 1:
The patent transitions from planar transistors to vertical JFETs, utilizing the third dimension (vertical stacking) to provide sufficient switching voltage and current while minimizing the planar footprint. The vertical channel structure allows current flow in the vertical direction rather than lateral direction, enabling high drive capability in a compact area.
Solution Approach 2:
The patent changes the geometric parameters of the transistor structure by forming a vertical channel with length extending into the substrate depth rather than laterally across the surface. This parameter change from lateral to vertical orientation enables high conductance while maintaining small planar dimensions.
2Power
If larger drive transistors are used to provide sufficient switching voltage and current, then memristor switching performance improves, but the device area increases
Solution Approach 1:
The invention uses vertical JFETs where the channel extends vertically into the substrate rather than laterally across the surface. This dimensional change allows the device to achieve high switching capability without increasing planar footprint, as the effective channel length is achieved through vertical depth rather than lateral width.
Solution Approach 2:
The vertical JFET structure nests the channel region within the substrate depth, utilizing the vertical space beneath the surface. This nesting approach allows the channel to occupy the vertical dimension while keeping the planar footprint minimal, effectively hiding the channel length in the third dimension.
3Reliability
If channel width is increased to provide higher conductance, then voltage drop is reduced, but planar surface area increases
Solution Approach 1:
The patent achieves increased effective channel width by wrapping the channel around the vertical gate structure in three dimensions. The channel forms a U-shaped or annular structure that surrounds the gate, providing increased conductive path length and effective width without increasing the planar footprint, as the expansion occurs in the vertical and radial directions rather than laterally.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The vertical JFET driver device achieves higher conductance and lower voltage drop, enabling higher switching voltage and current for memristor arrays, addressing the challenges of area footprint and performance in memristor-based applications.
Implementation Method 1
The channel region is formed of an epitaxial layer of a second semiconductor wrapped around the vertical gate region. Vertical source regions are formed on both sides of a first end of the vertical gate region, and vertical drain regions are formed on both sides of a second end of the vertical gate region.
Implementation Method 2
An epitaxial layer of a second semiconductor is grown to form a channel region.
Data Source
AI summary
Devices and methods are provided. In one aspect, a device for driving a memristor array includes a substrate including a well having a bottom layer, a first wall and a second wall. The substrate is formed of a strained layer of a first semiconductor material. A vertical JFET is formed in the well. The vertical JFET includes a vertical gate region formed in a middle portion of the well with a gate region height less than a depth of the well. A channel region is formed of an epitaxial layer of a second semiconductor wrapped around the vertical gate region. Vertical source regions are formed on both sides of a first end of the vertical gate region, and vertical drain regions are formed on both sides of a second end of the vertical gate region.