Semiconductor Gate Pattern CD Control via Mask Trimming
Solution Overview
Problem
The existing methods for forming gate patterns in semiconductor devices face challenges in controlling critical dimensions (CD) between cell and peripheral regions, particularly in dynamic random access memory (DRAM) fabrication, due to differences in pattern densities causing loading effects and resulting in enlarged CD in peripheral regions.
Innovation Solution
A method involving the formation of specific mask patterns and photoresist patterns, followed by trimming and etching processes, is employed to control CD in both cell and peripheral regions, including the use of plasma etch processes and selective gas use to reduce the width of hard mask patterns and buffer layers, thereby minimizing CD increases and maintaining desired dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single mask process is used to form gate patterns in both cell region and peripheral region, then the process is simple and efficient, but the critical dimension (CD) control is poor due to loading effects in peripheral region
Solution Approach 1:
The patent divides the mask pattern formation into two separate processes: a first mask process for the cell region and a second mask process for the peripheral region. This segmentation allows independent optimization of each region's pattern formation, enabling precise CD control in the peripheral region while maintaining high productivity through automated alignment with the first mask process.
2Ease of manufacture
If photoresist patterns are formed with large spacing distance in peripheral region, then the pattern formation is easier, but loading effects cause polymer accumulation on sidewalls and CD enlargement
Solution Approach 1:
The patent applies a preliminary trimming process to the hard mask pattern in the peripheral region before the main etch process. This trimming action预先 removes excess material and prevents polymer accumulation during subsequent etching, thereby preventing CD enlargement while maintaining the ease of forming patterns with larger spacing.
3Ease of operation
If the spacing distance between patterns is increased in peripheral region, then the manufacturing is easier, but the CD of gate pattern is enlarged due to loading effect
Solution Approach 1:
The patent applies different processing conditions to different regions: the cell region receives standard processing while the peripheral region receives specialized trimming processing. This local quality approach allows the peripheral region to maintain easier manufacturing conditions with larger spacing while compensating for the resulting CD enlargement through region-specific process optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively controls CD in both cell and peripheral regions, reducing the CD in peripheral regions and preventing excessive width formation, thus enabling the fabrication of high-speed semiconductor devices with precise pattern formation.
Implementation Method 1
performing a first plasma etch process to reduce a width of the hard mask pattern in the peripheral region
Implementation Method 2
forming a photoresist pattern exposing the PMOS region
Data Source
AI summary
A method for fabricating semiconductor device includes forming an etch target layer over a substrate including a cell region and a peripheral region, forming a first mask pattern having a first portion and a second portion over the etch target layer in the cell region and forming a second mask pattern having a first portion and a second portion over the etch target layer in the peripheral region, forming a photoresist pattern over the cell region, trimming the first portion of the second mask pattern, removing the photoresist pattern and the second portion of the first mask pattern and the second portion of the second mask pattern, and etching the etch target layer to form a pattern in the cell region and a pattern in the peripheral region.