Semiconductor Channel Layer Inclined Geometry for Integration
Solution Overview
Problem
The challenge in semiconductor devices is to increase the degree of integration while resolving disconnection phenomena in the lower portion of the channel layer and reducing the thickness of the channel layer to enhance data processing capacity.
Innovation Solution
A semiconductor device is designed with gate electrodes and interlayer insulating layers alternately stacked on a substrate, featuring a channel layer that penetrates through these layers and includes a gate dielectric layer, where the channel layer has inclined planes narrowing towards the substrate, and a method of manufacturing involves forming epitaxial layers and sacrificial spacer layers to create recessed regions for improved channel layer formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the channel layer thickness is reduced to increase integration degree, then the data processing capacity is improved, but disconnection phenomenon occurs in the lower portion of the channel layer
Solution Approach 1:
The channel layer is divided into two distinct regions: a first region with substantially parallel side surfaces extending vertically, and a second region with inclined side surfaces narrowing toward the substrate. This segmentation allows each region to serve different functions - the first region provides structural support and electrical connection, while the second region reduces overall thickness for higher integration.
Solution Approach 2:
Different geometric configurations are applied to different portions of the channel layer. The upper portion (first region) maintains a uniform width with parallel sides to ensure stable electrical properties, while the lower portion (second region) features inclined sides that narrow toward the substrate to reduce disconnection risks and improve contact with underlying structures.
2Productivity
If the channel layer thickness is reduced to enhance data processing capacity, then the integration degree is improved, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
A gate dielectric layer is formed on the substrate before the channel layer is deposited. This preliminary action provides a well-defined interface and control layer that facilitates precise formation of the channel layer with the desired complex geometry, including both the parallel-sided first region and the inclined-sided second region.
Solution Approach 2:
The channel layer geometry transitions from a simple two-dimensional planar structure to a three-dimensional structure with varying cross-sections. The inclusion of inclined side surfaces in the second region adds dimensional complexity that enables better control over thickness and connection properties while maintaining manufacturing feasibility through standardized deposition processes.
Data Source
AI summary
A semiconductor device includes gate electrodes and interlayer insulating layers alternately stacked on a substrate, a channel layer penetrating through the gate electrodes and the interlayer insulating layers, and a gate dielectric layer disposed on an external surface of the channel layer between the gate electrodes and the channel layer. In addition, the channel layer includes a first region extended in a direction perpendicular to a top surface of the substrate and a second region connected to the first region in a lower portion of the first region and including a plane inclined with respect to the top surface of the substrate.