ONO Integration into Logic CMOS Process
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Solution Overview
Problem
The integration of non-volatile memory devices, such as SONOS FETs, into the baseline MOSFET manufacturing process is complex and requires multiple mask sets, increasing costs and impacting the baseline process, particularly due to the need for precise control of thicknesses and geometries.
Innovation Solution
Simultaneously forming the gate dielectric layer of a MOS device and the top ONO layer of a non-volatile memory device, integrating the ONO dielectric stack into the MOSFET manufacturing process without altering the thermal budget or affecting the channel dopant profile, allowing for the simultaneous formation of gate and blocking dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If ONO dielectric stack is integrated into MOSFET manufacturing process, then non-volatile memory device functionality is achieved, but process complexity increases and requires multiple mask sets
Solution Approach 1:
The patent combines the formation of the ONO dielectric stack with the existing MOSFET gate dielectric layer formation process. The oxide-nitride-oxide structure is integrated into the same processing steps used to create the gate dielectric, eliminating the need for separate mask sets and process steps for non-volatile memory regions.
Solution Approach 2:
The gate dielectric layer formation process is designed to serve dual purposes: creating the gate dielectric for standard MOSFETs in logic regions and simultaneously forming the ONO dielectric stack for non-volatile memory devices in memory regions. This multi-functional approach allows a single process to achieve both device types without additional complexity.
2Adaptability or versatility
If separate process steps are used for ONO integration, then non-volatile memory structure is formed, but manufacturing cost increases
Solution Approach 1:
The patent merges the ONO stack formation with the MOSFET gate dielectric formation into a single integrated process. By using the same deposition and thermal processing steps for both structures, the patent eliminates redundant manufacturing operations and reduces overall production costs.
Solution Approach 2:
The manufacturing process is designed with universal steps that serve both logic and memory device fabrication. The gate dielectric formation process simultaneously creates the functional dielectric for MOSFETs and the ONO stack for non-volatile memory, maximizing resource utilization and minimizing per-device manufacturing cost.
3Adaptability or versatility
If baseline MOSFET process is altered for ONO integration, then non-volatile memory device is formed, but channel dopant profile integrity is compromised
Solution Approach 1:
The patent segments the substrate into distinct logic regions and memory regions with different device structures. The ONO stack is formed only in memory regions while the baseline MOSFET process continues unchanged in logic regions. This spatial segmentation allows process differentiation without affecting the overall process flow or dopant profiles in logic areas.
Solution Approach 2:
The patent applies local quality by forming the ONO dielectric stack specifically in non-volatile memory device regions while maintaining the standard gate dielectric formation in logic MOSFET regions. The process parameters and layer structures are locally optimized for each region type, ensuring that changes in memory regions do not impact the dopant profiles or performance of logic device regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the integration of non-volatile memory devices into the MOSFET process, reducing costs and maintaining the integrity of the baseline MOSFET fabrication process by avoiding changes to the channel dopant profile and thermal budget.
Implementation Method 1
performing a thermal oxidation to simultaneously form the gate dielectric layer of the MOS device and the blocking dielectric layer of the non-volatile memory device
Data Source
Figure 1A~1B
Figure 1C~1D
Figure 2A
AI summary
Disclosed is a method comprising: forming above a surface on a substrate a stack of gate layers including at least two dielectric layers separated by at least one gate layer; forming a nonvolatile memory device in a first region of the stack of gate layers comprising: forming a first opening extending from a top surface of the stack of gate layers to a lower surface of the stack of gate layers; forming on sidewalls of the first opening a charge-trapping layer; and forming on inside sidewalls of the charge-trapping layer a thin layer of semiconducting material, and substantially filling the first opening with a dielectric material separated from the stack of gate layers by the thin layer of semiconducting material the charge-trapping layer; and forming a MOS devices in a second region of the stack of gate layers.